MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 1696

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M–P
LOE (LBC GPCM output enable) signal, 13-6
LPBSE (LBC parity byte select) signal, 13-7
LSYNC_IN (LBC DLL synchronization in) signal, 13-8
LSYNC_OUT (LBC DLL synchronization out) signal, 13-8
LWE[0:3] (LBC GPCM write enable) signals, 13-6
M
MA[0:14] (DDR address bus) signals, 8-7
MAC functionality, see eTSEC, MAC functionality
Machine check
Master control register, 10-55
MBA[0:1] (DDR logical bank address) signals, 8-7
MCAS (DDR column address strobe) signal, 8-8
MCK[0:5] (DDR clock output complement) signals, 8-10
MCK[0:5] (DDR clock output) signals, 8-10
MCKE[0:3] (DDR clock enable) signals, 8-10
MCP (processor machine check) signal, 9-8
MCS[0:3] (DDR chip select) signals, 8-8
MDEU
MDIC[0:1] (DDR driver impedance calibration) signals, 8-9
Index-10
voltage selection, 23-31
ZBT SRAM interface, 13-99, 13-104
MCP (processor machine check) signal, 9-8
mcp summary register (MCPSUMR), 23-26
SRESET (soft reset) signal, 4-8
context registers, 10-143
data size register, 10-137, 10-142
FIFOs, 10-146
interrupt control register, 10-141
interrupt status register, 10-137, 10-139
key registers, 10-146
key size register, 10-136
mode register, 10-98, 10-132
reset control register, 10-137
signal timing, 13-80
synchronous UPWAIT (early transfer acknowledge),
UPM mode
UPM requests, 13-75
chip select signal timing, 13-84
data timing, 13-87
general purpose signal timing, 13-85
LGPL[0:5] timing (LAST), 13-88
loop control, 13-85
RAM word definition, 13-80
REDO, 13-86
wait mechanism (WAEN), 13-88
registers, 13-19, 13-20
exception requests, 13-77
memory access requests, 13-76
refresh timer requests, 13-77
software requests, 13-77
13-89
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
MDM[0:8] (DDR SDRAM data output mask) signals, 8-9
MDQ[0:8] (DDR data bus strobe) signals, 8-6, 8-61
MDVAL (DDR/LBC debug mode data valid) signal, 4-23,
MECC[0:5] (DDR error correcting code) signals as debug,
MECC[0:7] (DDR error correcting code) signals, 4-23, 8-7
Memory maps
Memory space
Message digest execution unit (MDEU), 10-132
Message interrupts, see Interrupt controller (PIC), message
MODT[0:3] (DDR on-die termination) signals, 8-9
MRAS (DDR row address strobe) signal, 8-8
MSRCID[0:4] (DDR/LBC debug source ID) signals, 4-23,
MWE (DDR write enable) signal, 8-8, 8-9
P
PCI Express Base Specification, Rev. 1.0a
CCSR memory, 2-4
configuration, control, and status registers, 4-3
DDR controller, 8-10
debug, watchpoint, and trace buffer registers, 25-9
device memory map
DMA, 15-5
DUART, 12-3
ECM, 7-3
eTSEC, 14-14
global utilities, 23-3
GPIO, 22-2
I
interrupt controller (PIC), 9-9
L2 cache/SRAM, 6-8
LBC, 13-9
PCI/PCI-X, 16-11
performance monitor, 24-3
USB interface, 21-4–21-5, ??–A-19
PCI/PCI-X addressing, 16-47
see PCI Express controller
2
C, 11-4
13-8, 25-3, 25-6
25-3, 25-7
accessing CCSR memory from external masters, 2-11
CCSR map, complete list of memory-mapped registers
CCSR organization, 2-11
CCSR registers, 2-10–2-14
device-specific utilities, 2-13
general utilities registers, 2-12
programmable interrupt controller (PIC) space, 2-13
illegal interaction between local access windows and
address translation and mapping, 2-3
overview and example, 2-1
interrupts
13-8, 25-3, 25-7
(by offset), 2-14
DDR SDRAM chip selects, 2-9
Freescale Semiconductor
Index