MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 1520

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MPC8536-RDK

Manufacturer Part Number
MPC8536-RDK
Description
BOARD REF COMEXPRESS MPC8536
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr
Datasheets

Specifications of MPC8536-RDK

Contents
CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Global Utilities
Table 23-20
23.4.1.18 Exception Reset Control Register (ECTRSTCR)
Shown in
to checkstop.
Table 23-21
23.4.1.19 Automatic Reset Status Register (AUTORSTSR)
Shown in
23-28
Offset 0x098
Reset
Offset 0x09C
Reset
W
R
W
R RST_
RST_CKSTP_EN
13–31
Figure
Figure
Bits
0–8
CKSTP
10
11
12
5–31
Bits
9
1–3
w1c
describes the bit settings of RSTRSCR.
describes the bit settings of ECTRSTCR.
0
4
0
0
23-18, the ECTRSTCR contains control bits for the exception reset of core in response
23-19, the AUTORSTSR contains the automatic reset status bits for core 0 and core 1.
1
CKSTP_OUT_DIS
RST_CKSTP_EN
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
NFLSH_RR
WDT_RR
SW_RR
BS_RR
Name
Figure 23-19. Automatic Reset Status Register (AUTORSTSR)
Figure 23-18. Exception Reset Control Register (ECTRSTCR)
3
Name
1
RST_
WRS
w1c
4
3
5
CKSTP_OUT_DIS
Table 23-21. ECTRSTCR Field Descriptions
Table 23-20. RSTRSCR Field Descriptions
7
Reserved
NAND Flash ECC error during boot reset request.
Boot sequence reset request
Watchdog timer reset request in the core . Occurs when TSR[WRS] = 10 for
the core and a watchdog reset condition is reached.
Software settable reset request
Reserved
RST_
MPIC
Enable automatic reset of core in response to core checkstop
Reserved
Disable assertion of CKSTP_OUT pin
Reserved
w1c
4
8
9
11
5
CORE
RST_
w1c
All zeros
12
All zeros
13
Description
Description
15
READY
16
17
19
DPSLP
RST_
w1c
20
Freescale Semiconductor
21
Access: Mixed
Access: Mixed
31
31

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