MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 694

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Local Bus Controller
Table 13-33
varied.
13.4.2.3
The banks selected to work with the GPCM support an option to drive the LCSn signal with different
timings (with respect to the external address/data bus). LCSn can be driven in any of the following ways:
13-52
•
Simultaneous with the latched memory address. (This refers to the externally latched address and
not the address timing on LAD. That is, the chip select does not assert during LALE).
TRLX
Option Register Attributes
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
lists the signal timing parameters for a GPCM write access as the option register attributes are
Chip-Select Assertion Timing
XACS
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
ACS
00
10
11
00
10
11
00
10
11
00
10
11
00
10
11
00
10
11
00
10
11
00
10
11
Table 13-33. GPCM Write Control Signal Timing
CSNT
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
t
AWCS
1¼
1½
1¼
1½
¼
½
¼
½
0
0
1
2
0
0
1
2
0
0
2
3
0
0
2
3
1¾+2×SCY
1½+2×SCY
1½+2×SCY
1¼+2×SCY
¾+2×SCY
¾+2×SCY
2+2×SCY
2+2×SCY
1+2×SCY
1+2×SCY
3+2×SCY
3+2×SCY
1¾+SCY
1½+SCY
1½+SCY
1¼+SCY
¾+SCY
¾+SCY
Signal Timing (LCLK clock cycles)
2+SCY
2+SCY
1+SCY
1+SCY
2+SCY
2+SCY
t
CSWP
t
AWE
1
1
1
1
1
2
1
1
1
1
1
2
1
2
2
1
2
3
1
2
2
1
2
3
t
WEN
1¼
1¼
¼
¼
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Freescale Semiconductor
2¾+2×SCY
2¾+2×SCY
2¾+2×SCY
3¾+2×SCY
2+2×SCY
3+2×SCY
3+2×SCY
2+2×SCY
3+2×SCY
4+2×SCY
3+2×SCY
3+2×SCY
1¾+SCY
1¾+SCY
1¾+SCY
2¾+SCY
2+SCY
2+SCY
2+SCY
2+SCY
2+SCY
3+SCY
2+SCY
2+SCY
t
WC