MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 1078

Manufacturer Part Number

BOARD REF COMEXPRESS MPC8536

Manufacturer

Freescale Semiconductor

PowerQUICC ™r

CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

PCI Bus Interface

Figure 16-51

Figure 16-52

A PCI transaction may be terminated by either the initiator or the target. The initiator is ultimately

responsible for concluding all transactions, regardless of the cause of the termination. All transactions are

concluded when PCI_FRAME and PCI_IRDY are both negated, indicating the bus is idle.

Normally, a master initiates termination by negating PCI_FRAME and asserting PCI_IRDY. This

indicates to the target that the final data phase is in progress. The final data transfer occurs when both

PCI_TRDY and PCI_IRDY are asserted. The transaction is considered complete when data is transferred

Transaction Termination

illustrates a PCI single-beat write transaction.

illustrates a PCI burst write transaction.

Master-Initiated Termination

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

Figure 16-51. PCI Single-Beat Write Transaction

Figure 16-52. PCI Burst Write Transaction

Byte Enables 1 Byte Enables 2

Byte Enables

Byte Enables 3

Freescale Semiconductor