MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 1052

Manufacturer Part Number

BOARD REF COMEXPRESS MPC8536

Manufacturer

Freescale Semiconductor

PowerQUICC ™r

CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

PCI Bus Interface

core_fault_in, which causes the core to generate a machine check interrupt, unless it is disabled (by

clearing HID1[RFXE]). If RFXE is zero and this error occurs, the appropriate parity detect and

master-abort bits in ERR_DR must be cleared and the appropriate enable bits in ERR_EN must be set to

ensure that an interrupt is generated. For more information, see

Implementation-Dependent Register 1 (HID1).”

Offset 0xE08

error enable

Trgt abort error capture disable

OWMSV error capture disable

ORMSV error capture disable

IRMSV error capture disable

SCM error capture disable

TOE error capture disable

describes ERR_EN fields. Note that uncorrectable read errors may cause the assertion of

PCI Error Enable Register (ERR_EN)

error enable

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

Table 16-16. ERR_CAP_DR Field Descriptions (continued)

Figure 16-17. PCI Error Enable Register (ERR_EN)

error enable

Disable capture for target abort errors

Disable capture for outbound write memory space violation errors

Disable capture for outbound read memory space violation errors

Disable capture for inbound read memory space violation errors

Disable capture for split completion message errors

Disable capture for time-out errors

Section 6.10.2, “Hardware

error enable

error enable

Freescale Semiconductor

Access: Read/Write

error enable