MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 1379

Manufacturer Part Number

BOARD REF COMEXPRESS MPC8536

Manufacturer

Freescale Semiconductor

PowerQUICC ™r

CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

DWords 1–8 constitute eight slots of transaction control and status. Each transaction description includes:

The host controller uses the information in each transaction description, plus the endpoint information

contained in the first three DWords of the buffer page pointer list, to execute a transaction on the USB.

Freescale Semiconductor

Status results field

Transaction length (bytes to send for OUT transactions and bytes received for IN transactions).

Buffer offset. The PG and Transaction n Offset fields are used with the buffer pointer list to

construct the starting buffer address for the transaction.

Link Pointer Correspond to memory address signals [31:5], respectively. This field points to another isochronous

iTD Transaction Status and Control List

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

transaction descriptor (iTD/siTD) or queue head (QH).

Reserved, should be cleared. These bits are reserved and their value has no effect on operation.

Software should initialize this field to zero.

Indicates to the host controller whether the item referenced is an iTD, siTD or a QH. This allows the host

controller to perform the proper type of processing on the item after it is fetched. Value encodings are:

00 iTD (isochronous transfer descriptor)

01 QH (queue head)

10 siTD (split transaction isochronous transfer descriptor)

11 FSTN (frame span traversal node)

1 Link Pointer field is not valid.

0 Link Pointer field is valid.

Table 21-38. Next Schedule Element Pointer

Universal Serial Bus Interfaces