MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 525

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
0–50
Bits
51
52
53
54
55
56
57
58
59
60
61
62
63
Names
OFU
ERE
DSE
OFE
KSE
IFO
ME
IFE
CE
AE
—
IE
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
Internal Error. An internal processing error was detected while performing encryption.
0 Internal error enabled
1 Internal error disabled
Early Read Error. The AFEU Register was read while the AFEU was performing
encryption.
0 Early read error enabled
1 Early read error disabled
Context Error. An AFEU key register, the key size register, data size register, mode
register, or context memory was modified while AFEU was performing encryption.
0 Context error enabled
1 Context error disabled
Key Size Error. A value outside the bounds 1–16 bytes was written to the AFEU key
size register
0 Key size error enabled
1 Key size error disabled
Data Size Error. An inconsistent value was written to the AFEU data size register:
0 Data Size error enabled
1 Data size error disabled
Mode Error. An illegal value was detected in the mode register.
0 Mode error enabled
1 Mode error disabled
Address Error. An illegal read or write address was detected within the AFEU address
space.
0 Address error enabled
1 Address error disabled
Output FIFO Error. The AFEU Output FIFO was detected non-empty upon write of
AFEU data size register
0 Output FIFO non-empty error enabled
1 Output FIFO non-empty error disabled
Input FIFO Error. The AFEU Input FIFO was detected non-empty upon generation of
done interrupt.
0 Input FIFO non-empty error enabled
1 Input FIFO non-empty error disabled
Reserved
Input FIFO Overflow. The AFEU Input FIFO was pushed while full.
0 Input FIFO overflow error enabled
1 Input FIFO overflow error disabled
Output FIFO Underflow. The AFEU Output FIFO was read while empty.
0 Output FIFO underflow error enabled
1 Output FIFO underflow error disabled
Reserved
Table 10-41. AFEU Interrupt Mask Register
Description
Security Engine (SEC) 3.0
10-95