MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 1386

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
Queue element transfer descriptors must be aligned on 32-byte boundaries.
21.5.5.1
The first DWord of an element transfer descriptor is a pointer to another transfer element descriptor.
21.5.5.2
The second DWord of a queue element transfer descriptor is used to support hardware-only advance of the
data stream to the next client buffer on short packet. To be more explicit the host controller will always use
this pointer when the current qTD is retired due to short packet.
21-52
1
dt
31
31–5
31–5
Bits
Bits
4–1
4–1
Host controller read/write; all others read-only.
1
0
0
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Next qTD
Alternate Next
Pointer
qTD Pointer
Name
—
T
Name
Next qTD Pointer
Alternate Next qTD Pointer
—
T
Total Bytes to Transfer
This field contains the physical memory address of the next qTD to be processed and corresponds to
memory address signals [31:5], respectively.
Reserved, should be cleared. These bits are reserved and their value has no effect on operation.
Terminate. Indicates to the host controller that there are no more valid entries in the queue.
0 Pointer is valid (points to a valid transfer element descriptor)
1 Pointer is invalid
Table 21-52. qTD Alternate Next Element Transfer Pointer (DWord 1)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Buffer Pointer (Page 0)
Buffer Pointer (Page 1)
Buffer Pointer (Page 2)
Buffer Pointer (Page 3)
Buffer Pointer (Page 4)
This field contains the physical memory address of the next qTD to be processed in the event that
the current qTD execution encounters a short packet (for an IN transaction). The field corresponds
to memory address signals [31:5], respectively.
Reserved, should be cleared. These bits are reserved and their value has no effect on operation.
Terminate. Indicates to the host controller that there are no more valid entries in the queue.
0 Pointer is valid (points to a valid transfer element descriptor)
1 Pointer is invalid
Table 21-51. qTD Next Element Transfer Pointer (DWord 0)
Figure 21-39. Queue Element Transfer Descriptor (qTD)
Alternate Next qTD Pointer
1
Next qTD Pointer
ioc C_Page
15
14 13 12 11 10
Description
Description
1
Cerr
1
PID Code
9
0000_0000_0000
0000_0000_0000
0000_0000_0000
0000_0000_0000
8
Current Offset
7
6
5
Freescale Semiconductor
Status
1
4
0000
0000
3
1
2
1
T 0x00
T 0x04
0
0x0C
0x1C
Offset
0x08
0x10
0x14
0x18