MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 184

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset, Clocking, and Initialization
4.4.3.5
The core speed configuration inputs, shown in
with the core clock frequencies in use. The default setting is appropriate for the core operating above
800 MHz; for low-speed operation (core at or below 800 MHz) this POR configuration input should be
low during HRESET. If this configuration is not set properly, behavior of the system may be unreliable.
Note that the value latched on this signal during POR is accessible through the memory-mapped
PORDEVSR, described in
4.4.3.6
The device defines the default boot ROM address range to be 8 Mbytes at address 0x0_FF80_0000 to
0x0_FFFF_FFFF. However, which peripheral interface handles these boot ROM accesses can be selected
at power on.
The boot ROM location inputs, shown in
to the boot vector and the default boot ROM region of the local address map are directed to the interface
specified by these inputs.
Boot from eSPI or SD/MMC is supported by the MPC8536E using an on-chip ROM which contains the
basic eSPI or eSDHC device driver and the code to perform block copy from eSPI EEPROM or SD/MMC
card to DDR memory. Selecting on-chip ROM in boot ROM location will cause the e500 CPU to fetch
data from the on-chip ROM.
4-14
LWE0/LBS0/LFWE
Functional
Default (1)
Signal
Core Speed Configuration
Boot ROM Location
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reset Configuration
Section 23.4.1.4, “POR Device Status Register (PORDEVSR).”
cfg_core_speed
Name
Table 4-13. Core Speed Configuration
Table
(Binary)
Value
Table 4-13
4-14, select the physical location of boot ROM. Accesses
0
1
Core frequency at or below 800 MHz
Core frequency above 800 MHz
configure internal logic for proper operation
Meaning
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