MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 1109

Manufacturer Part Number

BOARD REF COMEXPRESS MPC8536

Manufacturer

Freescale Semiconductor

PowerQUICC ™r

CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

The fields of the PCI Express configuration register are described in

The PCI Express PME and message detect register, shown in

PME events that are detected by the PCI Express controller. This register is a write-1-to-clear type register.

The fields of the PCI Express PME and message detect register are described in

Freescale Semiconductor

Offset 0x020

PCI Express Power Management Event and Message Registers

Figure 17-7. PCI Express PME and Message Detect Register (PEX_PME_MES_DR)

PCI Express PME and Message Detect Register (PEX_PME_MES_DR)

PME turn off. This bit indicates the detection of a PME_Turn_Off message. This bit is only valid in EP mode.

1 A PME_Turn_Off_message is detected

0 No PME_Turn_Off message detected

Reserved. Note that during normal operation, this bit may be set (falsely). The bit may be ignored and

cleared (w1c) without consequence.

Sense ASPM Control. This bit controls the default value of ASPM of PEX Link Control Register’s bit 0. See

Section 17.3.9.11, “PCI Express Link Control Register—0x5C,”

Slot Present. This bit controls the default value of the PCI Express capabilities register [slot] bit. See

Section 17.3.9.6, “PCI Express Capabilities Register—0x4E,”

Slot Clock Configuration. This bit controls the default value of the PCI Express link status register [SCC] bit.

Section 17.3.9.12, “PCI Express Link Status Register—0x5E,”

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

Table 17-9. PEX_PME_MES_DR Field Descriptions

Table 17-8. PEX_CONFIG Field Descriptions

for more information.

for more information.

17-7, logs inbound messages and

for more information.

PCI Express Interface Controller