DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 56

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

2–48
Table 2–46. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
Arria II GX FPGA Development Board Reference Manual
U23.A1
U23.B1
U23.C1
U23.D1
U23.D2
U23.A2
U23.C2
U23.A3
U23.B3
U23.C3
U23.D3
U23.C4
U23.A5
U23.B5
U23.C5
U23.D7
U23.D8
U23.A7
U23.B7
U23.C7
U23.C8
U23.A8
U23.G1
U23.H8
U23.B6
U23.F2
Board Reference
Flash
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus (die select)
Data bus
The flash interface consists of a single synchronous flash memory device, providing
64 Mbyte with a 16-bit data bus. This device is part of the shared FSM bus which
connects to the flash memory, SRAM, and MAX II CPLD EPM2210 System Controller.
The parameter blocks are 32 K and main blocks are 128 K. The blocks are located at
the bottom of the address space.
This 16-bit data memory interface can sustain burst read operations at up to 52 MHz
for a throughput of 832 Mbps. The write performance is 270 µs for a single word and
310 µs for a 32-word buffer. The erase time is 800 ms for a 128 K main block.
Table 2–46
names and types are relative to the Arria II GX device in terms of I/O setting and
direction.
Description
lists the flash pin assignments, signal names, and functions. The signal
Schematic Signal Name
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
FSM_A16
FSM_A17
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
FSM_A23
FSM_A24
FSM_A25
FSM_A1
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A6
FSM_A7
FSM_A8
FSM_A9
FSM_D0
I/O Standard
2.5-V
February 2011 Altera Corporation
Chapter 2: Board Components
Arria II GX Device
Pin Number
M13
D29
D20
A23
B24
C24
H19
K21
G23
H21
A19
J21
L13
E25
F21
J19
L21
F25
F26
F10
C8
N9
P7
R4
K4
J3
Memory