DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 40

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

2–32
Table 2–36. Ethernet PHY Component Reference and Manufacturing Information
Arria II GX FPGA Development Board Reference Manual
U24
Board Reference
High-Speed Mezzanine Cards
f
Ethernet PHY BASE-T device
Table 2–36
information.
The development board contains two HSMC interfaces—port A and port B. The
HSMC port B is only available if the Arria II GX FPGA development board is
populated with the EP2AGX260 device. By default, the board is populated with the
EP2AGX125 device and only HSMC port A is available. HSMC port A interface
supports both single-ended and differential signaling while HSMC port B interface
only supports single-ended signaling. The HSMC interface also allows JTAG, SMB,
clock outputs and inputs, as well as power for compatible HSMC cards. The HSMC is
an Altera-developed open specification, which allows you to expand the functionality
of the development board through the addition of daughtercards (HSMCs).
For more information about the HSMC specification such as signaling standards,
signal integrity, compatible connectors, and mechanical information, refer to the
Speed Mezzanine Card (HSMC) Specification
The HSMC connector has a total of 172 pins, including 120 signal pins, 39 power pins,
and 13 ground pins. The ground pins are located between the two rows of signal and
power pins, acting both as a shield and a reference. The HSMC host connector is
based on the 0.5 mm-pitch QSH/QTH family of high-speed, board-to-board
connectors from Samtec. There are three banks in this connector. Bank 1 has every
third pin removed as done in the QSH-DP/QTH-DP series. Bank 2 and bank 3 have
all the pins populated as done in the QSH/QTH series.
Figure 2–10
connector's three banks.
Figure 2–10. HSMC Signal and Bank Diagram
Description
lists the Ethernet PHY interface component reference and manufacturing
shows the bank arrangement of signals with respect to the Samtec
Marvell
Semiconductor
Manufacturer
8 RX Channels CDR
8 TX Channels CDR
CLKIN2, CLKOUT2
CLKIN1, CLKOUT1
CLKIN0, CLKOUT0
D[3:0] + LVDS
D(79.40)
D(39:0)
Bank 2
Bank 3
Bank 1
Power
Power
LVDS
manual.
JTAG
SMB
-or-
-or-
88E1111-B2-CAAIC000
Manufacturing
Part Number
February 2011 Altera Corporation
Chapter 2: Board Components
Components and Interfaces
www.marvell.com
Manufacturer
Website
High