DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 41

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

Chapter 2: Board Components
Components and Interfaces
Table 2–37. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
February 2011 Altera Corporation
J2.17
J2.18
J2.19
J2.20
J2.21
J2.22
J2.23
J2.24
J2.25
J2.26
J2.27
J2.28
J2.29
J2.30
J2.31
J2.32
J2.33
J2.34
J2.35
J2.36
J2.37
J2.38
J2.39
J2.40
J2.41
J2.42
J2.43
J2.44
Reference
Board
1
Transceiver TX bit 3
Transceiver RX bit 3
Transceiver TX bit 3n
Transceiver RX bit 3n
Transceiver TX bit 2
Transceiver RX bit 2
Transceiver TX bit 2n
Transceiver RX bit 2n
Transceiver TX bit 1
Transceiver RX bit 1
Transceiver TX bit 1n
Transceiver RX bit 1n
Transceiver TX bit 0
Transceiver RX bit 0
Transceiver TX bit 0n
Transceiver RX bit 0n
Management serial data
Management serial clock
JTAG clock signal
JTAG mode select signal
JTAG data output
JTAG data input
Dedicated CMOS clock out
Dedicated CMOS clock in
Dedicated CMOS I/O bit 0
Dedicated CMOS I/O bit 1
Dedicated CMOS I/O bit 2
Dedicated CMOS I/O bit 3
The HSMC interface has programmable bi-directional I/O pins that can be used as
2.5-V LVCMOS, which is 3.3-V LVTTL-compatible. These pins can also be used as
various differential I/O standards including, but not limited to, LVDS, mini-LVDS,
and RSDS with up to 17 full-duplex channels.
As noted in the
single-ended I/O standards are only guaranteed to function when mixed according to
either the generic single-ended pin-out or generic differential pin-out.
Table 2–37
functions.
Description
lists the HSMC port A interface pin assignments, signal names, and
High Speed Mezzanine Card (HSMC) Specification
Schematic Signal
JTAG_HSMA_TDO
JTAG_HSMA_TDI
HSMA_CLKOUT0
HSMA_CLKIN0
HSMA_TX_P3
HSMA_RX_P3
HSMA_TX_N3
HSMA_RX_N3
HSMA_TX_P2
HSMA_RX_P2
HSMA_TX_N2
HSMA_RX_N2
HSMA_TX_P1
HSMA_RX_P1
HSMA_TX_N1
HSMA_RX_N1
HSMA_TX_P0
HSMA_RX_P0
HSMA_TX_N0
HSMA_RX_N0
HSMA_SDA
HSMA_SCL
JTAG_TCK
JTAG_TMS
HSMA_D0
HSMA_D1
HSMA_D2
HSMA_D3
Name
Arria II GX FPGA Development Board Reference Manual
I/O Standard
1.5-V PCML
2.5-V
manual, LVDS and
Pin Number
Arria II GX
Device
AP17
M31
M32
N33
N34
R33
R34
U33
U34
N25
K31
L33
K32
L34
P31
P32
T31
T32
L24
P10
M1
R1
R6
T1
—
—
L1
K1
2–33