DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 16

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

2–8
Table 2–7. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 2 of 5)
Arria II GX FPGA Development Board Reference Manual
clk1_od[0]
clk1_od[1]
clk1_od[2]
clk1_os[0]
clk1_os[1]
clk1_pr[0]
clk1_pr[1]
clk1_rstn
clk100_cpld
clk155_oe
clk2_ce
clk2_od[0]
clk2_od[1]
clk2_od[2]
clk2_os[0]
clk2_os[1]
clk2_pr[0]
clk2_pr[1]
clk2_rstn
csense_adc_f0
csense_csn[0]
csense_csn[1]
csense_sck
csense_sdi
csense_sdo
ddr2_scl
ddr2_sda
ep_clk
ep_cs
ep_di
ep_do
factory_user
flash_advn
flash_cen
flash_clk
flash_oen
flash_rdy_bsyn
flash_resetn
Schematic Signal Name
I/O Standard
2.5-V
Pin Number
EPM2210
M14
M15
M16
H12
N16
N14
N13
N15
G16
H15
H16
H14
H13
D15
P15
P14
K15
K16
L13
J14
J15
J16
F15
M2
M1
M3
M7
M6
N1
N2
D8
L3
L2
L1
E1
C8
C9
E7
EP2AGX125
Pin Number
M3
N4
K5
R3
N3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T4
Programmable oscillator 1 output divider 0
Programmable oscillator 1 output divider 1
Programmable oscillator 1 output divider 2
Programmable oscillator 1 output select 0
Programmable oscillator 1 output select 1
Programmable oscillator 1 prescaler 0
Programmable oscillator 1 prescaler 1
Programmable oscillator 1 reset
100 MHz clock input
155.52 MHz oscillator enable
Programmable oscillator 2 chip select
Programmable oscillator 2 output divider 0
Programmable oscillator 2 output divider 1
Programmable oscillator 2 output divider 2
Programmable oscillator 2 output select 0
Programmable oscillator 2 output select 1
Programmable oscillator 2 prescaler 0
Programmable oscillator 2 prescaler 1
Programmable oscillator 2 reset
Power monitor frequency
Power monitor 0 chip select
Power monitor 1 chip select
Power monitor serial peripheral interface (SPI)
clock
Power monitor SPI data in
Power monitor SPI data out
DDR2 SODIMM EEPROM clock
DDR2 SODIMM EEPROM data
EEPROM clock
EEPROM chip select
EEPROM data in
EEPROM data out
Load factory or user design at power-up
FSM bus flash memory address valid
FSM bus flash memory chip enable
FSM bus flash memory clock
FSM bus flash memory output enable
FSM bus flash memory ready
FSM bus flash memory reset
MAX II CPLD EPM2210 System Controller
Description
February 2011 Altera Corporation
Chapter 2: Board Components