DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 31

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

Chapter 2: Board Components
Clock Circuitry
Figure 2–7. Arria II GX FPGA Development Board Clock Outputs
Table 2–21. Arria II GX FPGA Development Board Clock Outputs
February 2011 Altera Corporation
SMA
Samtec HSMC
Samtec HSMC
Samtec HSMC
Samtec HSMC
Connector
Arria II GX FPGA Clock Outputs
7 6 5 4 3 2 1 0
SMA
HSMB_CLKOUT_P[2]/N[2]
(Differential SSTL-15)
DDR3_CLK_P/N
Schematic Signal Name
HSMA_CLKOUT_P1
HSMA_CLKOUT_N1
HSMA_CLKOUT_P2
HSMA_CLKOUT_N2
HSMA_CLKOUT0
HSMB_CLKOUT0
CLOCK_SMA
Figure 2–7
Table 2–21
CLKOUT_SMA
(2.5 V)
(LVDS)
HSMA_CLKOUT0
HSMA_CLKOUT_P[1]/N[1]
(2.5 V)
shows the Arria II GX FPGA development board clock outputs.
lists the clock outputs for the Arria II GX FPGA development board.
(LVDS)
PLL 2
PLL 1
Q 3
6 B
AG30
HSMA_CLKOUT_P[2]/N[2]
W12
AD7
AD6
P10
V12
F23
Pin
EP2AGX125EF35
Q 2
6 A
PLL
(LVDS)
5
LVDS or 2.5-V
LVDS or 2.5-V
I/O Standard
2.5-V
2.5-V
2.5-V
PLL
Q 1
5 A
6
7 6 5 4 3 2 1 0
PLL 3
PLL 4
FPGA CMOS output or general purpose I/O (GPIO)
FPGA CMOS output or GPIO
LVDS output or two 2.5-V CMOS outputs.
LVDS output or two 2.5-V CMOS outputs.
FPGA CMOS output or GPIO
Q 0
5 B
Arria II GX FPGA Development Board Reference Manual
(Differential SSTL-18)
DDR2_CLK_P/N[1:0]
Description
HSMB_CLKOUT0
(2.5 V)
2–23