DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 30

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

2–22
Table 2–20. Arria II GX FPGA Development Board Clock Inputs (Part 2 of 2)
Arria II GX FPGA Development Board Reference Manual
SMA or
100.000 MHz
(Default
Frequency)
125.000 MHz
(Default
Frequency)
Samtec HSMC
Samtec HSMC
Samtec HSMC
Samtec HSMC
PCI Express
Edge
Notes to
(1) CDCM61001 has a default frequency of 100 MHz, but can also be set by the MAX II CPLD to frequencies of 125 MHz and 156.25 MHz.
(2) CDCM61004 has a default frequency of 125 MHz, but can also be set by the MAX II CPLD to frequencies of 100 MHz and 156.25 MHz.
(3) Transceiver Q3 is only available when the Arria II GX FPGA development board is populated with the EP2AGX260 device.
(4) HSMB is only available when the Arria II GX FPGA development board is populated with the EP2AGX260 device.
Source
Table
(1)
(2)
2–20:
Schematic Signal Name
CLK_REF_Q3_P
CLK_REF_Q3_N
HSMB_CLKIN0
CLK_REF_Q1_1_N
CLK_REF_Q1_2_N
CLKIN_REF_Q2_P
CLKIN_REF_Q2_N
CLK_REF_Q1_1_P
CLK_REF_Q1_2_P
HSMA_CLKIN_P1
HSMA_CLKIN_N1
HSMA_CLKIN_P2
HSMA_CLKIN_N2
PCIE_REFCLK_P
PCIE_REFCLK_N
CLKIN_BOT_P
CLKIN_BOT_N
CLKIN_TOP_P
CLKIN_TOP_N
HSMA_CLKIN0
(4)
(3)
(3)
AK19
AA29
AA30
AP17
AP16
AE29
AE30
AJ19
W29
W30
U29
U30
N29
N30
K18
F18
F17
J18
Pin
U6
U5
LVDS or LVTTL
LVDS or LVTTL
I/O Standard
LVTTL
LVTTL
LVDS
LVDS
HCSL
Input to the fan-out buffer (U33) which drives
LVDS input to the bottom edge of PLL input.
Input to the fan-out buffer (U33) which drives
LVDS input to the transceiver Q2 reference
clock input with 100  OCT.
Programmable oscillator which drives LVDS
input to the top edge of PLL input.
Programmable oscillator which drives LVDS
input to the transceiver Q1 reference clock
input with 100  OCT.
Programmable oscillator which drives LVDS
input to the transceiver Q3 reference clock
input with 100  OCT.
Single-ended input from the installed HSMC
port A cable or board.
LVDS input from the installed HSMC port A
cable or board. Can also support two LVTTL
inputs.
LVDS input from the installed HSMC port A
cable or board. Can also support two LVTTL
inputs.
Single-ended input from the installed HSMC
port B cable or board.
High-Speed Current Steering Logic (HCSL)
input from the PCI Express edge connector.
Description
February 2011 Altera Corporation
Chapter 2: Board Components
Clock Circuitry