DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 51

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

Chapter 2: Board Components
Memory
Table 2–42. DDR2 SODIMM Pin Assignments, Signal Names and Functions (Part 2 of 4)
February 2011 Altera Corporation
J7.5
J7.7
J7.17
J7.19
J7.4
J7.6
J7.14
J7.16
J7.10
J7.13
J7.11
J7.23
J7.25
J7.35
J7.37
J7.20
J7.22
J7.36
J7.38
J7.26
J7.31
J7.29
J7.43
J7.45
J7.55
J7.57
J7.44
J7.46
J7.56
J7.58
J7.52
J7.51
J7.49
J7.61
J7.63
J7.73
J7.75
J7.62
Board Reference
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Write mask byte lane 0
Data strobe P byte lane 0
Data strobe N byte lane 0
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Write mask byte lane 1
Data strobe P byte lane 1
Data strobe N byte lane 1
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Write mask byte lane 2
Data strobe P byte lane 2
Data strobe N byte lane 2
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Description
Schematic Signal
DDR2_DQSN0
DDR2_DQSN1
DDR2_DQSN2
DDR2_DQS0
DDR2_DQ10
DDR2_DQ11
DDR2_DQ12
DDR2_DQ13
DDR2_DQ14
DDR2_DQ15
DDR2_DQS1
DDR2_DQ16
DDR2_DQ17
DDR2_DQ18
DDR2_DQ19
DDR2_DQ20
DDR2_DQ21
DDR2_DQ22
DDR2_DQ23
DDR2_DQS2
DDR2_DQ24
DDR2_DQ25
DDR2_DQ26
DDR2_DQ27
DDR2_DQ28
DDR2_DQ0
DDR2_DQ1
DDR2_DQ2
DDR2_DQ3
DDR2_DQ4
DDR2_DQ5
DDR2_DQ6
DDR2_DQ7
DDR2_DM0
DDR2_DQ8
DDR2_DQ9
DDR2_DM1
DDR2_DM2
Name
Arria II GX FPGA Development Board Reference Manual
1.8-V SSTL Class I
I/O Standard
Pin Number
Arria II GX
Device
AM29
AM28
AM25
AM26
AM24
AM23
AM22
AM21
AG21
AP29
AN28
AK22
AP27
AP25
AG22
AH21
AN24
AP24
AK25
AP23
AH20
AG19
AP21
AP22
AN21
AP18
AH19
AL29
AJ24
AJ25
AJ23
AL24
AE19
AL25
AL21
AL20
AJ21
AE18
2–43