DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 39

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

Chapter 2: Board Components
Components and Interfaces
Figure 2–9. RGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY
Table 2–35. Ethernet PHY Pin Assignments, Signal Names and Functions
February 2011 Altera Corporation
U24.8
U24.23
U24.25
U24.24
U24.28
U24.2
U24.95
U24.92
U24.93
U24.91
U24.94
U24.11
U24.12
U24.14
U24.16
U24.9
Board Reference
10/100/1000 Ethernet
10/100/1000 Mbps
Ethernet MAC
RGMII transmit clock
Management bus interrupt
Management bus control
Management bus data
Device reset
RGMII receive clock
RGMII receive data
RGMII receive data
RGMII receive data
RGMII receive data
RGMII receive control
RGMII transmit data
RGMII transmit data
RGMII transmit data
RGMII transmit data
RGMII transmit control
A Marvell 88E1111 PHY device is used for 10/100/1000 BASE-T Ethernet connection.
The device is an auto-negotiating Ethernet PHY with an RGMII interface to the FPGA.
The MAC function must be provided in the FPGA for typical networking
applications. The Marvell 88E1111 PHY uses 2.5-V and 1.1-V power rails and requires
a 25 MHz reference clock driven from a dedicated oscillator. It interfaces to a HALO
HFJ11-1G02E model RJ45 with internal magnetics that can be used for driving copper
lines with Ethernet traffic.
Figure 2–9
PHY.
Table 2–35
RGMII Interface
TXD[3:0]
RXD[3:0]
Description
shows the RGMII interface between the FPGA (MAC) and Marvell 88E1111
lists the Ethernet PHY interface pin assignments.
Marvell 88E1111
Device
PHY
Schematic Signal
ENET_GTX_CLK
ENET_RX_D[0]
ENET_RX_D[1]
ENET_RX_D[2]
ENET_RX_D[3]
ENET_TX_D[0]
ENET_TX_D[1]
ENET_TX_D[2]
ENET_TX_D[3]
ENET_RESETn
ENET_RX_CLK
ENET_RX_DV
ENET_TX_EN
ENET_INTn
ENET_MDIO
ENET_MDC
Name
Transformer
Arria II GX FPGA Development Board Reference Manual
I/O Standard
2.5-V
RJ45
Arria II GX Device
Pin Number
M20
D25
D18
N20
D17
G22
G21
G20
K20
E21
E24
E22
C25
F24
J20
V6
2–31