DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 55

KIT DEV ARRIA II GX FPGA 2AGX125

DK-DEV-2AGX125N

Manufacturer Part Number
DK-DEV-2AGX125N
Description
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer
Altera
Series
Arria II GXr
Type
FPGAr

Specifications of DK-DEV-2AGX125N

Contents
Board, Cables, CD, DVD, Power Supply
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Arria
Silicon Core Number
EP2
Silicon Family Name
Arria II GX
Rohs Compliant
Yes
For Use With/related Products
EP2AGX125EF35
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2600

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DK-DEV-2AGX125N
Manufacturer:
Altera
Quantity:
135
Part Number:
DK-DEV-2AGX125N
Manufacturer:
ALTERA
0
Chapter 2: Board Components
Memory
Table 2–44. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3)
Table 2–45. SSRAM Component Reference and Manufacturing Information
February 2011 Altera Corporation
U22.F2
U22.G1
U22.G2
U22.J1
U22.J2
U22.K1
U22.K2
U22.L1
U22.L2
U22.M1
U22.M2
U22.A8
U22.B9
U22.A9
U22.A7
U22.B5
U22.A5
U22.A4
U22.B4
U22.A3
U22.B6
U22.N11
U22.C11
U22.C1
U22.N1
U22.B7
U22.R1
U22.B8
U22.H11
Board Reference
U22
Board Reference
Standard synchronous pipelined
SCD, 512K × 36, 200 MHz
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Address status controller
Address status processor
Address valid
Byte write enable
Byte lane 0 write enable
Byte lane 1 write enable
Byte lane 2 write enable
Byte lane 3 write enable
Chip enable
Clock
Data bus parity byte lane 0
Data bus parity byte lane 1
Data bus parity byte lane 2
Data bus parity byte lane 3
Global write enable
Mode
Output enable
Sleep
Table 2–45
Description
Description
lists the SSRAM component reference and manufacturing information.
Schematic Signal Name
ISSI Inc.
Manufacturer
SRAM_DQP0
SRAM_DQP1
SRAM_DQP2
SRAM_DQP3
SRAM_ADSCn
SRAM_ADSPn
SRAM_ADVn
SRAM_BEN0
SRAM_BEN1
SRAM_BEN2
SRAM_BEN3
SRAM_CE1n
SRAM_MODE
SRAM_WEn
SRAM_CLK
SRAM_GWn
SRAM_OEn
FSM_D21
FSM_D22
FSM_D23
FSM_D24
FSM_D25
FSM_D26
FSM_D27
FSM_D28
FSM_D29
FSM_D30
FSM_D31
SRAM_ZZ
IS61VPS51236A-200B3
Arria II GX FPGA Development Board Reference Manual
Manufacturing
Part Number
I/O Standard
2.5-V
(Connects to the MAX II
CPLD EPM2210 System
Arria II GX Device
Pin Number
Controller)
Manufacturer
www.issi.com
R11
D19
H12
H13
A24
B22
C22
D10
T10
A18
B18
C19
B21
A21
C21
A22
C10
A20
J11
J13
E10
J12
K12
B27
Website
D9
P9
P4
E9
2–47

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