DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 49

KIT DEV ARRIA II GX FPGA 2AGX125

DK-DEV-2AGX125N

Manufacturer Part Number
DK-DEV-2AGX125N
Description
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer
Altera
Series
Arria II GXr
Type
FPGAr

Specifications of DK-DEV-2AGX125N

Contents
Board, Cables, CD, DVD, Power Supply
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Arria
Silicon Core Number
EP2
Silicon Family Name
Arria II GX
Rohs Compliant
Yes
For Use With/related Products
EP2AGX125EF35
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2600

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DK-DEV-2AGX125N
Manufacturer:
Altera
Quantity:
135
Part Number:
DK-DEV-2AGX125N
Manufacturer:
ALTERA
0
Chapter 2: Board Components
Memory
Table 2–40. DDR3 Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)
Table 2–41. DDR3 Component Reference and Manufacturing Information
February 2011 Altera Corporation
U13.E3
U13.F7
U13.F2
U13.F8
U13.H3
U13.H8
U13.G2
U13.H7
U13.E7
U13.F3
U13.G3
U13.D7
U13.C3
U13.C8
U13.C2
U13.A7
U13.A2
U13.B8
U13.A3
U13.D3
U13.C7
U13.B7
U13
Board Reference
Board Reference
DDR2 SODIMM
8 M × 16 × 8 banks, 667M, CL9 Micron
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Write mask byte lane 0
Data strobe P byte lane 0
Data strobe N byte lane 0
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Write mask byte lane 1
Data strobe P byte lane 1
Data strobe N byte lane 1
Table 2–41
There is a DDR2 200-pin SODIMM device, providing 1-GB single-rank DIMM with a
64-bit data bus. This memory interface runs at a maximum fequency of 333 MHz for a
maximum theoretical bandwidth of over 42.6 Gbps. The internal bus in the FPGA is
typically 2 or 4 times the width at full rate or half rate respectively. For example, a
333 MHz 64-bit interface becomes a 166.5 MHz 256-bit bus.
Description
Description
lists the DDR3 component reference and manufacturing information.
Manufacturer
Schematic Signal
DDR3_DQS_P0
DDR3_DQS_N0
DDR3_DQS_P1
DDR3_DQS_N1
DDR3_DQ10
DDR3_DQ11
DDR3_DQ12
DDR3_DQ13
DDR3_DQ14
DDR3_DQ15
DDR3_DQ0
DDR3_DQ1
DDR3_DQ2
DDR3_DQ3
DDR3_DQ4
DDR3_DQ5
DDR3_DQ6
DDR3_DQ7
DDR3_DM0
DDR3_DQ8
DDR3_DQ9
DDR3_DM1
Name
MT41J64M16LA-15E
Arria II GX FPGA Development Board Reference Manual
Manufacturing
Part Number
1.5-V SSTL Class I
I/O Standard
www.micron.com
Manufacturer
Website
Pin Number
Arria II GX
Device
G14
D13
D12
G15
G13
J16
K17
L16
F15
F13
J15
K15
F12
E12
B7
A6
A3
A4
B3
B9
A2
B4
2–41

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