DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 29

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

Chapter 2: Board Components
Clock Circuitry
Clock Circuitry
Figure 2–6. Arria II GX FPGA Development Board Clock Inputs
Table 2–20. Arria II GX FPGA Development Board Clock Inputs (Part 1 of 2)
February 2011 Altera Corporation
U25
3 .3 V
Source
Arria II GX FPGA Clock Inputs
Control signals route
CLK 2 _ RSTn
CLK 2 _ OS 1
to MAX II
CLK 2 _ OS 0
CLK 2 _ CE
7 6 5 4 3 2 1 0
CLK 2 _ PR 1
CLK 2 _ PR 0
CLK 2 _ OD 2
CLK 2 _ OD 1
CLK 2 _ OD 0
SMA
Schematic Signal Name
This section describes the board's clock inputs and outputs.
The development board has two types of clock inputs—global clock inputs and
transceiver reference clock inputs.
Figure 2–6
Table 2–20
board.
CLOCK_SMA
CLK_155_P
CLK_155_N
CDCM61004RHB
(Default 125 MHz)
Low Jitter Clock
Generator*
155.52 M
HSMA CLK_IN_P[2]/N[2]
25 MHz
shows the Arria II GX FPGA development board clock inputs.
Crystal
shows the external clock inputs for the Arria II GX FPGA development
(LVPECL)
XIN 2
PLL 2
PLL 1
Q 3
6 B
(LVDS)
EP2AGX125EF35
(LVDS)
(LVDS)
6 A
Q 2
* CDCM6100x can be set to output frequencies
PLL
of 100 MHz, 125 MHz, 156.25 MHz.
R29
R30
Pin
5
PLL
Q 1
5 A
6
7 6 5 4 3 2 1 0
ENET_RX_CLK
I/O Standard
PLL 3
PLL 4
(2.5 V)
LVPECL
Q 0
5 B
CLK_SEL
(LVDS)
REFCLK INPUT
SMA
(LVPECL )
(LVDS)
155.52 MHz oscillator which drives the
transceiver Q2 reference clock input with
100  OCT.
Arria II GX FPGA Development Board Reference Manual
2-to-4 buffer
SMA
HSMB_CLK_IN0
HSMA_CLK_IN0
XIN 1
25 MHz
Crystal
(Default 100 MHz)
CDCM61001RHB
3 .3 V
Low Jitter Clock
Generator*
EPM2210 System Controller
Description
MAX II CPLD
50 M
(2.5 V)
100 M
(2.5 V)
3 .3 V
2–21