DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 44

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

2–36
Table 2–37. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)
Table 2–38. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
Arria II GX FPGA Development Board Reference Manual
J2.160
D4
D5
J1.17
J1.18
J1.19
J1.20
J1.21
J1.22
J1.23
J1.24
J1.25
J1.26
J1.27
J1.28
J1.29
J1.30
J1.31
J1.32
J1.33
J1.34
J1.35
J1.36
J1.37
J1.38
J1.39
J1.40
J1.41
J1.42
J1.43
Reference
Reference
Board
Board
Transceiver TX bit 3
Transceiver RX bit 3
Transceiver TX bit 3n
Transceiver RX bit 3n
Transceiver TX bit 2
Transceiver RX bit 2
Transceiver TX bit 2n
Transceiver RX bit 2n
Transceiver TX bit 1
Transceiver RX bit 1
Transceiver TX bit 1n
Transceiver RX bit 1n
Transceiver TX bit 0
Transceiver RX bit 0
Transceiver TX bit 0n
Transceiver RX bit 0n
Management serial data
Management serial clock
JTAG clock signal
JTAG mode select signal
JTAG data output
JTAG data input
Dedicated CMOS clock out
Dedicated CMOS clock in
Dedicated CMOS I/O bit 0
Dedicated CMOS I/O bit 1
Dedicated CMOS I/O bit 2
HSMC port A presence detect
User LED to show RX data activity on
HSMC port A
User LED to show TX data activity on
HSMC port A
Table 2–38
functions when the board uses an EP2AGX260 device.
Description
Description
lists the HSMC port B interface pin assignments, signal names, and
Schematic Signal
Schematic Signal
JTAG_HSMB_TDO
JTAG_HSMB_TDI
HSMB_CLKOUT0
HSMA_PSNT_n
HSMA_RX_LED
HSMA_TX_LED
HSMB_CLKIN0
HSMB_TX_P3
HSMB_RX_P3
HSMB_TX_N3
HSMB_RX_N3
HSMB_TX_P2
HSMB_RX_P2
HSMB_TX_N2
HSMB_RX_N2
HSMB_TX_P1
HSMB_RX_P1
HSMB_TX_N1
HSMB_RX_N1
HSMB_TX_P0
HSMB_RX_P0
HSMB_TX_N0
HSMB_RX_N0
HSMB_SDA
HSMB_SCL
JTAG_TCK
JTAG_TMS
HSMB_D0
HSMB_D1
HSMB_D2
Name
Name
I/O Standard
I/O Standard
1.5-V PCML
2.5-V
2.5-V
February 2011 Altera Corporation
Chapter 2: Board Components
Components and Interfaces
Pin Number
Pin Number
Arria II GX
Arria II GX
Device
Device
AG30
AH29
AH30
AK27
AJ27
AP16
AK30
B31
C33
B32
C34
D31
D32
G33
G34
H31
H32
N25
C29
E33
E34
F31
F32
J33
J34
L24
U3
N5
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