DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 15

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

Chapter 2: Board Components
MAX II CPLD EPM2210 System Controller
MAX II CPLD EPM2210 System Controller
Figure 2–3. MAX II CPLD EPM2210 System Controller Block Diagram
Table 2–7. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 1 of 5)
February 2011 Altera Corporation
clk_enable
clk_sel
clk1_ce
Schematic Signal Name
Embedded
Measurement
Blaster
Results
PC
Power
The specific I/O resources available in the Arria II GX EP2AGX260EF35 device are
listed in
available in the Arria II GX EP2AGX260EF35 device to support an extra transceiver
quadrant and additional I/O banks.
The board utilizes the EPM2210 System Controller, an Altera MAX II CPLD, for the
following purposes:
■
■
■
■
■
Figure 2–3
and external circuit connections as a block diagram.
Table 2–7
Controller. The signal names and functions are relative to the MAX II device (U32).
Encoder
FPGA configuration from flash memory
Power consumption monitoring
Virtual JTAG interface for PC-based GUI
Control registers for clocks
Control registers for remote system update
I/O Standard
Controller
LTC2418
“General User Input/Output” on page
2.5-V
lists the I/O signals present on the MAX II CPLD EPM2210 System
illustrates the MAX II CPLD EPM2210 System Controller's functionality
JTAG Control
Virtual-JTAG
SLD-HUB
Pin Number
EPM2210
K14
N3
P2
Calculations
Power
EP2AGX125
Pin Number
Decoder
—
—
—
MAX II CPLD EPM2210 System Controller
DIP - clock oscillator enable
DIP - clock select SMA or oscillator
Programmable oscillator 1 chip select
Arria II GX FPGA Development Board Reference Manual
Information
2–24. A second HSMC port is
Register
Control
Register
PFL
Description
GPIO
SSRAM
FLASH
A2GX
2–7