DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 20

KIT DEV ARRIA II GX FPGA 2AGX125

DK-DEV-2AGX125N

Manufacturer Part Number
DK-DEV-2AGX125N
Description
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer
Altera
Series
Arria II GXr
Type
FPGAr

Specifications of DK-DEV-2AGX125N

Contents
Board, Cables, CD, DVD, Power Supply
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Arria
Silicon Core Number
EP2
Silicon Family Name
Arria II GX
Rohs Compliant
Yes
For Use With/related Products
EP2AGX125EF35
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2600

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DK-DEV-2AGX125N
Manufacturer:
Altera
Quantity:
135
Part Number:
DK-DEV-2AGX125N
Manufacturer:
ALTERA
0
2–12
Configuration, Status, and Setup Elements
Arria II GX FPGA Development Board Reference Manual
Configuration
This section describes the board's configuration, status, and setup elements.
This section describes the FPGA, flash memory, and MAX II CPLD EPM2210 System
Controller device programming methods supported by the Arria II GX FPGA
development board. The Arria II GX FPGA development board supports the
following three configuration methods:
FPGA Programming over Embedded USB-Blaster
The board implements a USB-Blaster using a USB Type-B connector (J6), a FTDI USB
2.0 PHY device (U15), and an Altera MAX IIZ CPLD (U10). This allows the
configuration of the FPGA using a USB cable directly connected between the USB port
on the board (J6) and a USB port of a PC running the Quartus II software. The JTAG
chain is normally mastered by the embedded USB-Blaster found in the MAX IIZ
CPLD EPM240Z embedded USB-Blaster.
The embedded USB-Blaster automatically disables when an external USB-Blaster is
connected to the JTAG chain.
Embedded USB-Blaster is the default method for configuring the FPGA at any
time using the Quartus II Programmer in JTAG mode with the supplied USB cable.
External USB-Blaster for configuring the FPGA using the external USB-Blaster.
Flash memory download for configuring the FPGA using stored images from the
flash memory on either power-up or pressing the load image push-button switch
(PB5).
Configuration, Status, and Setup Elements
February 2011 Altera Corporation
Chapter 2: Board Components

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