DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 48

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

2–40
Table 2–40. DDR3 Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
Arria II GX FPGA Development Board Reference Manual
U13.N3
U13.P7
U13.P3
U13.N2
U13.P8
U13.P2
U13.R8
U13.R2
U13.T8
U13.R3
U13.L7
U13.R7
U13.N7
U13.T3
U13.T7
U13.M2
U13.N8
U13.M3
U13.K3
U13.K9
U13.L2
U13.K1
U13.J3
U13.T2
U13.L3
U13.J7
U13.K7
Board Reference
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Bank address bus
Bank address bus
Bank address bus
Column address select
Clock enable
Chip select
Termination enable
Row address select
Reset
Write enable
Clock P
Clock N
Table 2–40
names and types are relative to the Arria II device in terms of I/O setting and
direction.
Description
lists the DDR3 pin assignments, signal names, and functions. The signal
Schematic Signal
DDR3_CAS_n
DDR3_RAS_n
DDR3_RST_n
DDR3_CLK_P
DDR3_CLK_N
DDR3_CS_n
DDR3_WE_n
DDR3_A10
DDR3_A11
DDR3_A12
DDR3_A13
DDR3_A14
DDR3_BA0
DDR3_BA1
DDR3_BA2
DDR3_CKE
DDR3_ODT
DDR3_A0
DDR3_A1
DDR3_A2
DDR3_A3
DDR3_A4
DDR3_A5
DDR3_A6
DDR3_A7
DDR3_A8
DDR3_A9
Name
1.5-V SSTL Class I
Differential 1.5-V
I/O Standard
SSTL Class I
February 2011 Altera Corporation
Chapter 2: Board Components
Pin Number
Arria II GX
Device
M16
M17
G16
H18
G17
D11
D16
D15
G18
A12
F16
C13
K14
A11
E15
B15
C12
C16
B10
A10
E16
A13
A15
B13
B12
A7
A8
Memory