DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 21

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

Chapter 2: Board Components
Configuration, Status, and Setup Elements
Figure 2–4. JTAG Chain
February 2011 Altera Corporation
SW4.6
USB Type-B
Connector
(on install)
Figure 2–4
Each jumper shown in
of the board. To connect a device or interface in the chain, remove the corresponding
shunt from the jumper. Install a shunt on each of the four jumper positions to only
have the FPGA in the chain.
The MAX II CPLD EPM2210 System Controller must be in the chain to use some of the
GUI interfaces. For this setting, remove the left-most jumper shunt from the JTAG
chain header (J9).
Flash Memory Programming
Flash memory programming is possible through a variety of methods using the Arria
II GX device.
DISABLE
J6
J9
GPIO
Embedded
illustrates the JTAG chain.
Blaster
JTAG Master
USB
PHY
HSMA_JTAG_EN
HSMB_JTAG_EN
MAX_JTAG_EN
PCIE_JTAG_EN
GPIO
GPIO
GPIO
GPIO
TCK
TMS
TDO
Figure 2–4
TDI
Analog
Switch
Analog
Switch
Analog
Switch
Analog
Switch
JTAG Connector
10-pin
is located in the JTAG chain header (J9) on the front
J5
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
TMS
TDI
TDO
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
TCK
JTAG Master/Slave
JTAG Master/Slave
JTAG Master/Slave
Arria II GX FPGA Development Board Reference Manual
JTAG Slave
MAX II CPLD
JTAG Slave
PCI Express
EP2AGX125
Connector
Controller
EPM2210
HSMC
Port A
HSMC
Port B
FPGA
System
Edge
Motherboard
ENABLED
PCI Express
ALWAYS
(in chain)
Installed
Installed
Memory
HSMC
HSMC
Flash
Card
Card
2–13