EP1C3 ALTERA [Altera Corporation], EP1C3 Datasheet - Page 90

• Manufacturer Part Number: EP1C3
• Description: Cyclone FPGA Family
• Manufacturer: ALTERA [Altera Corporation]

Cyclone FPGA Family Data Sheet
Note to
(1)
90
1.8-V LVTTL
1.5-V LVTTL
3.3-V PCI
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
Decrease input delay to
internal cells
Decrease input delay to
input register
Increase delay to output
pin
Table 64. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins (Part 2 of 2)
Table 65. Cyclone IOE Programmable Delays on Column Pins
EP1C3 devices do not support the PCI I/O standard.
I/O Standard
Parameter
Tables 59
2 mA
8 mA
12 mA
2 mA
4 mA
8 mA
64:
On
Small
Medium
Large
On
On
Table 65
delays are controlled with the Quartus II software options listed in the
Parameter column.
Setting
Min
-6 Speed Grade
shows the adder delays for the IOE programmable delays. These
-6 Speed Grade
Min
6,606
5,112
4,862
8,380
7,437
6,888
1,175
1,799
1,363
2,115
1,820
1,330
Max
3,057
2,212
2,639
3,057
3,057
Max
552
-7 Speed Grade
Min
-7 Speed Grade
Min
7,267
5,623
5,348
9,218
8,180
7,576
1,292
1,979
1,499
2,326
2,001
1,463
Max
3,362
2,433
2,902
3,362
3,362
Max
607
-8 Speed Grade
Min
-8 Speed Grade
Min
Preliminary Information
Altera Corporation
10,055
7,927
6,134
5,834
8,923
8,264
1,409
2,158
1,635
2,537
2,183
1,595
Max
3,668
2,654
3,166
3,668
3,668
Max
662
Unit
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps