EP1C3 ALTERA [Altera Corporation], EP1C3 Datasheet - Page 46

• Manufacturer Part Number: EP1C3
• Description: Cyclone FPGA Family
• Manufacturer: ALTERA [Altera Corporation]

Cyclone FPGA Family Data Sheet
Figure 28. Row I/O Block Connection to the Interconnect
Notes to
(1)
(2)
46
The 21 data and control signals consist of three data out lines, io_dataout[2..0], three output enables,
io_coe[2..0], three input clock enables, io_cce_in[2..0], three output clock enables, io_cce_out[2..0],
three clocks, io_cclk[2..0], three asynchronous clear signals, io_caclr[2..0], and three synchronous clear
signals, io_csclr[2..0].
Each of the three IOEs in the row I/O block can have one io_datain input (combinatorial or registered) and one
comb_io_datain (combinatorial) input.
LAB Local
Interconnect
Figure
R4 Interconnects
to Adjacent LAB
Interconnect
Direct Link
28:
LAB
io_datain[2..0] and
comb_io_datain[2..0] (2)
C4 Interconnects
from Adjacent LAB
Interconnect
Direct Link
I/O Block Local
Interconnect
io_clk[5:0]
21
I/O Block
Contains up to
Row I/O Block
Row
Three IOEs
Preliminary Information
Altera Corporation
21 Data and
Control Signals
from Logic Array (1)