EP1C3 ALTERA [Altera Corporation], EP1C3 Datasheet - Page 25

• Manufacturer Part Number: EP1C3
• Description: Cyclone FPGA Family
• Manufacturer: ALTERA [Altera Corporation]

Preliminary Information
Altera Corporation
When configured as RAM or ROM, the designer can use an initialization
file to pre-load the memory contents.
Two single-port memory blocks can be implemented in a single M4K
block as long as each of the two independent block sizes is equal to or less
than half of the M4K block size.
The Quartus II software automatically implements larger memory by
combining multiple M4K memory blocks. For example, two 256
RAM blocks can be combined to form a 256 32-bit RAM block. Memory
performance does not degrade for memory blocks using the maximum
number of words allowed. Logical memory blocks using less than the
maximum number of words use physical blocks in parallel, eliminating
any external control logic that would increase delays. To create a larger
high-speed memory block, the Quartus II software automatically
combines memory blocks with LE control logic.
Parity Bit Support
The M4K blocks support a parity bit for each byte. The parity bit, along
with internal LE logic, can implement parity checking for error detection
to ensure data integrity. Designers can also use parity-size data words to
store user-specified control bits. Byte enables are also available for data
input masking during write operations.
Shift Register Support
The designer can configure M4K memory blocks to implement shift
registers for DSP applications such as pseudo-random number
generators, multi-channel filtering, auto-correlation, and cross-correlation
functions. These and other DSP applications require local data storage,
traditionally implemented with standard flip-flops, which can quickly
consume many logic cells and routing resources for large shift registers. A
more efficient alternative is to use embedded memory as a shift register
block, which saves logic cell and routing resources and provides a more
efficient implementation with the dedicated circuitry.
The size of a w m n shift register is determined by the input data width
(w), the length of the taps (m), and the number of taps (n). The size of a
w m n shift register must be less than or equal to the maximum number
of memory bits in the M4K block (4,608 bits). The total number of shift
register outputs (number of taps n
maximum data width of the M4K RAM block ( 36). To create larger shift
registers, multiple memory blocks are cascaded together.
width w) must be less than the
Cyclone FPGA Family Data Sheet
16-bit
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