EP1C3 ALTERA [Altera Corporation], EP1C3 Datasheet - Page 52

• Manufacturer Part Number: EP1C3
• Description: Cyclone FPGA Family
• Manufacturer: ALTERA [Altera Corporation]

Cyclone FPGA Family Data Sheet
Figure 33. Cyclone Device DQ & DQS Groups in 8 Mode
Note to
(1)
52
Each DQ group consists of one DQS pin, eight DQ pins, and one DM pin.
Figure
Top, Bottom, Left, or Right I/O Bank
33:
DDR SDRAM & FCRAM
Cyclone devices have dedicated circuitry for interfacing with DDR
SDRAM. All I/O banks support DDR SDRAM and FCRAM I/O pins.
However, the configuration input pins in bank 1 must operate at 2.5 V
because the SSTL-2 V
output pins (nSTATUS and CONF_DONE) and all the JTAG pins in I/O
bank 3 must operate at 2.5 V because the V
I/O banks 1, 2, 3, and 4 support DQS signals with DQ bus modes of 8.
For 8 mode, there are up to eight groups of programmable DQS and DQ
pins, I/O banks 1, 2, 3, and 4 each have two groups in the 324-pin and
400-pin FineLine BGA packages. Each group consists of one DQS pin, a set
of eight DQ pins, and one DM pin (see
set of eight DQ pins within that group.
DQ Pins
DQS Pin
CCIO
level is 2.5 V. Additionally, the configuration
Note (1)
Figure
CCIO
33). Each DQS pin drives the
level of SSTL-2 is 2.5 V.
Preliminary Information
DM Pin
Altera Corporation