EP1C3 ALTERA [Altera Corporation], EP1C3 Datasheet - Page 48

• Manufacturer Part Number: EP1C3
• Description: Cyclone FPGA Family
• Manufacturer: ALTERA [Altera Corporation]

Cyclone FPGA Family Data Sheet
Figure 30. Signal Path through the I/O Block
48
From Logic
To Logic
Array
Array
comb_io_datain
Row or Column
io_cce_out
io_clk[5..0]
io_dataout
io_cce_in
io_datain
io_caclr
io_csclr
io_cclk
io_coe
The pin’s datain signals can drive the logic array. The logic array drives
the control and data signals, providing a flexible routing resource. The
row or column IOE clocks, io_clk[5..0], provide a dedicated routing
resource for low-skew, high-speed clocks. The global clock network
generates the IOE clocks that feed the row or column I/O regions (see
“Global Clock Network & Phase-Locked Loops” on page
illustrates the signal paths through the I/O block.
Each IOE contains its own control signal selection for the following
control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset,
clk_in, and clk_out.
Data and
Selection
Control
Signal
oe
ce_in
ce_out
aclr/preset
sclr
clk_in
clk_out
dataout
Figure 31
To Other
IOEs
illustrates the control signal selection.
IOE
Preliminary Information
Altera Corporation
34).
Figure 30