EP1C3 ALTERA [Altera Corporation], EP1C3 Datasheet - Page 55

• Manufacturer Part Number: EP1C3
• Description: Cyclone FPGA Family
• Manufacturer: ALTERA [Altera Corporation]

Preliminary Information
Altera Corporation
Programmable Drive Strength
The output buffer for each Cyclone device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL and
LVCMOS standards have several levels of drive strength that the designer
can control. SSTL-3 class I and II, and SSTL-2 class I and II support a
minimum setting, the lowest drive strength that guarantees the I
of the standard. Using minimum settings provides signal slew rate control
to reduce system noise and signal overshoot.
settings for the I/O standards with drive strength control.
Open-Drain Output
Cyclone devices provide an optional open-drain (equivalent to an open-
collector) output for each I/O pin. This open-drain output enables the
device to provide system-level control signals (e.g., interrupt and write-
enable signals) that can be asserted by any of several devices.
LVTTL (3.3 V)
LVCMOS (3.3 V)
LVTTL (2.5 V)
LVTTL (1.8 V)
LVCMOS (1.5 V)
Table 14. Programmable Drive Strength
I/O Standard
I
OH
/I
Cyclone FPGA Family Data Sheet
OL
Current Strength Setting (mA)
Table 14
shows the possible
12
16
24
12
12
16
12
4
8
2
4
8
2
8
2
8
2
4
8
OH
/I
OL
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