EP1C3 ALTERA [Altera Corporation], EP1C3 Datasheet - Page 24

• Manufacturer Part Number: EP1C3
• Description: Cyclone FPGA Family
• Manufacturer: ALTERA [Altera Corporation]

Cyclone FPGA Family Data Sheet
24
Figure 13. Simple Dual-Port & Single-Port Memory Configurations
Note to
(1)
The memory blocks also enable mixed-width data ports for reading and
writing to the RAM ports in dual-port RAM configuration. For example,
the memory block can be written in 1 mode at port A and read out in 16
mode from port B.
The Cyclone memory architecture can implement fully synchronous RAM
by registering both the input and output signals to the M4K RAM block.
All M4K memory block inputs are registered, providing synchronous
write cycles. In synchronous operation, the memory block generates its
own self-timed strobe write enable (wren) signal derived from a global
clock. In contrast, a circuit using asynchronous RAM must generate the
RAM wren signal while ensuring its data and address signals meet setup
and hold time specifications relative to the wren signal. The output
registers can be bypassed. Pseudo-asynchronous reading is possible in the
simple dual-port mode of M4K blocks by clocking the read enable and
read address registers on the negative clock edge and bypassing the
output registers.
Two single-port memory blocks can be implemented in a single M4K block as long
as each of the two independent block sizes is equal to or less than half of the M4K
block size.
Figure
Simple Dual-Port Memory
Single-Port Memory (1)
13:
data[ ]
wraddress[ ]
wren
inclocken
inaclr
data[ ]
address[ ]
wren
inclocken
inaclr
inclock
inclock
rdaddress[ ]
outclocken
outclocken
outclock
outclock
outaclr
outaclr
Preliminary Information
rden
q[ ]
q[ ]
Altera Corporation