EP1C3 ALTERA [Altera Corporation], EP1C3 Datasheet - Page 47

• Manufacturer Part Number: EP1C3
• Description: Cyclone FPGA Family
• Manufacturer: ALTERA [Altera Corporation]

Preliminary Information
Altera Corporation
Figure 29. Column I/O Block Connection to the Interconnect
Notes to
(1)
(2)
The 21 data and control signals consist of three data out lines, io_dataout[2..0], three output enables,
io_coe[2..0], three input clock enables, io_cce_in[2..0], three output clock enables, io_cce_out[2..0],
three clocks, io_cclk[2..0], three asynchronous clear signals, io_caclr[2..0], and three synchronous clear
signals, io_csclr[2..0].
Each of the three IOEs in the column I/O block can have one io_datain input (combinatorial or registered) and
one comb_io_datain (combinatorial) input.
Local Interconnect
Figure
from Logic Array (1)
R4 Interconnects
I/O Block
Control Signals
29:
21 Data &
LAB Local
Interconnect
LAB
21
comb_io_datain[2..0]
C4 Interconnects
IO_datain[2:0] &
Column I/O Block
LAB
(2)
Cyclone FPGA Family Data Sheet
LAB
Column I/O
Block Contains
up to Three IOEs
io_clk[5..0]
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