EP1C3 ALTERA [Altera Corporation], EP1C3 Datasheet - Page 34

• Manufacturer Part Number: EP1C3
• Description: Cyclone FPGA Family
• Manufacturer: ALTERA [Altera Corporation]

Cyclone FPGA Family Data Sheet
Figure 21. Single-Port Mode
Global Clock
Network &
Phase-Locked
Loops
34
address[ ]
outclken
outclock
inclken
inclock
data[ ]
wren
6 LAB Row
Clocks
6
Cyclone devices provide a global clock network and up to two PLLs for a
complete clock management solution.
Global Clock Network
There are four dedicated clock pins (CLK[3..0], two pins on the left side
and two pins on the right side) that drive the global clock network, as
shown in
(DPCLK[7..0]) pins can also drive the global clock network.
The eight global clock lines in the global clock network drive throughout
the entire device. The global clock network can provide clocks for all
resources within the device IOEs, LEs, and memory blocks. The global
clock lines can also be used for control signals, such as clock enables and
synchronous or asynchronous clears fed from the external pin, or DQS
signals for DDR SDRAM or FCRAM interfaces. Internal logic can also
drive the global clock network for internally generated global clocks and
asynchronous clears, clock enables, or other control signals with large
fanout.
network.
D
ENA
D
ENA
Figure 22
Figure
Q
Q
22. PLL outputs, logic array, and dual-purpose clock
shows the various sources that drive the global clock
Generator
D
ENA
Pulse
Write
Q
Data In
Address
Write Enable
RAM/ROM
1,024
2,048
4,096
Data Out
256
512
16
8
4
2
1
D
ENA
Preliminary Information
Q
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