EP1C3 ALTERA [Altera Corporation], EP1C3 Datasheet - Page 53

• Manufacturer Part Number: EP1C3
• Description: Cyclone FPGA Family
• Manufacturer: ALTERA [Altera Corporation]

Preliminary Information
Altera Corporation
Table 13
Note to
(1)
A programmable delay chain on each DQS pin allows for either a 90°
phase shift (for DDR SDRAM), or a 72° phase shift (for FCRAM) which
automatically center-aligns input DQS synchronization signals within the
data window of their corresponding DQ data signals. The phase-shifted
DQS signals drive the global clock network. This global DQS signal clocks
DQ signals on internal LE registers.
These DQS delay elements combine with the PLL’s clocking and phase
shift ability to provide a complete hardware solution for interfacing to
high-speed memory.
The clock phase shift allows the PLL to clock the DQ output enable and
output paths. The designer should use the following guidelines to meet
133 MHz performance for DDR SDRAM and FCRAM interfaces:
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
Table 13. DQ Pin Groups
Device
EP1C3 devices in the 100-pin TQFP package do not have any DQ pin groups in I/O
bank 1.
The DQS signal must be in the middle of the DQ group it clocks
Resynchronize the incoming data to the logic array clock using
successive LE registers or FIFO buffers
LE registers must be placed in the LAB adjacent to the DQ I/O pin
column it is fed by
Table
shows the number of DQ pin groups per device.
13:
100-pin TQFP
144-pin TQFP
324-pin FineLine BGA
400-pin FineLine BGA
144-pin TQFP
240-pin PQFP
256-pin FineLine BGA
240-pin PQFP
256-pin FineLine BGA
324-pin FineLine BGA
324-pin FineLine BGA
400-pin FineLine BGA
Package
(1)
Number of 8 DQ
Pin Groups
Cyclone FPGA Family Data Sheet
3
4
8
8
4
4
4
4
4
8
8
8
Total DQ Pin
Count
24
32
64
64
32
32
32
32
32
64
64
64
53