EP1C3 ALTERA [Altera Corporation], EP1C3 Datasheet - Page 40

• Manufacturer Part Number: EP1C3
• Description: Cyclone FPGA Family
• Manufacturer: ALTERA [Altera Corporation]

Cyclone FPGA Family Data Sheet
Notes to
(1)
(2)
(3)
40
PLL Counter
Output
Dedicated
Clock Input
Pins
Dual-Purpose
Clock Pins
Table 10. Global Clock Network Sources
EP1C3 devices only have one PLL (PLL 1).
EP1C3 devices in the 100-pin TQFP package do not have dedicated clock pins CLK1 and CLK3.
EP1C3 devices in the 100-pin TQFP package do not have the DPCLK0, DPCLK1, or DPCLK5 pins.
Table
Source
10:
PLL1 G0
PLL1 G1
PLL2 G0
PLL2 G1
CLK0
CLK1
CLK2
CLK3
DPCLK0
DPCLK1
DPCLK2
DPCLK3
DPCLK4
DPCLK5
DPCLK6
DPCLK7
(2)
(2)
(3)
(3)
(3)
(1)
(1)
Table 10
devices.
Clock Multiplication & Division
Cyclone PLLs provide clock synthesis for PLL output ports using
m/(n
pre-scale divider, n, and is then multiplied by the m feedback factor. The
control loop drives the VCO to match f
unique post-scale counter to divide down the high-frequency VCO. For
multiple PLL outputs with different frequencies, the VCO is set to the
least-common multiple of the output frequencies that meets its frequency
specifications. Then, the post-scale dividers scale down the output
frequency for each output port. For example, if the output frequencies
required from one PLL are 33 and 66 MHz, the VCO is set to 330 MHz (the
least-common multiple in the VCO’s range).
GCLK0
v
v
v
post scale counter) scaling factors. The input clock is divided by a
shows the global clock network sources available in Cyclone
GCLK1
v
v
v
GCLK2
v
v
v
GCLK3
v
v
v
GCLK4
IN
v
v
v
(m/n). Each output port has a
GCLK5
v
v
v
Preliminary Information
Altera Corporation
GCLK6
v
v
v
GCLK7
v
v
v