EP1C3 ALTERA [Altera Corporation], EP1C3 Datasheet - Page 57

• Manufacturer Part Number: EP1C3
• Description: Cyclone FPGA Family
• Manufacturer: ALTERA [Altera Corporation]

Preliminary Information
Altera Corporation
Notes to
(1)
(2)
(3)
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI
LVDS
SSTL-2 class I and II
SSTL-3 class I and II
Differential SSTL-2
Table 15. Cyclone I/O Standards
EP1C3 devices do not support PCI.
EP1C3 devices in the 100-pin TQFP package do not support the LVDS I/O standard.
This I/O standard is only available on output clock pins (PLL_OUT pins).
I/O Standard
(2)
Table
(1)
15:
(3)
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Differential
Voltage-referenced
Voltage-referenced
Differential
Advanced I/O Standard Support
Cyclone device IOEs support the following I/O standards:
Table 15
Cyclone devices contain four I/O banks, as shown in
1 and 3 support all the I/O standards listed in
4 support all the I/O standards listed in
standard. I/O banks 2 and 4 contain dual-purpose DQS, DQ, and DM pins
to support a DDR SDRAM or FCRAM interface. I/O bank 1 can also
support a DDR SDRAM or FCRAM interface, however, the configuration
input pins in I/O bank 1 must operate at 2.5 V. I/O bank 3 can also
support a DDR SDRAM or FCRAM interface, however, all the JTAG pins
in I/O bank 3 must operate at 2.5 V.
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI
LVDS
SSTL-2 class I and II
SSTL-3 class I and II
Differential SSTL-2 class II (on output clocks only)
Type
describes the I/O standards supported by Cyclone devices.
Voltage (V
Input Reference
N/A
N/A
N/A
N/A
N/A
N/A
1.25
1.5
1.25
REF
) (V)
Voltage (V
Output Supply
Table 15
Cyclone FPGA Family Data Sheet
3.3
2.5
1.8
1.5
3.3
2.5
2.5
3.3
2.5
(V)
Table
CCIO
except the 3.3-V PCI
)
Figure
15. I/O banks 2 and
Voltage (V
Termination
35. I/O banks
Board
N/A
N/A
N/A
N/A
N/A
N/A
1.25
1.5
1.25
TT
) (V)
57