EP1C3 ALTERA [Altera Corporation], EP1C3 Datasheet - Page 73

• Manufacturer Part Number: EP1C3
• Description: Cyclone FPGA Family
• Manufacturer: ALTERA [Altera Corporation]

Preliminary Information
Altera Corporation
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) The Cyclone LVDS interface requires a resistor network outside of the transmitter channels.
(11) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
Power
Consumption
Timing Model
C
C
C
C
C
Table 38. Cyclone Device Capacitance
IO
LVDS
VREF
DPCLK
CLK
See the
Conditions beyond those listed in
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –0.5 V or overshoot to 4.6 V for input
currents less than 100 mA and periods shorter than 20 ns.
Maximum V
All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before V
powered.
Typical values are for T
This value is specified for normal device operation. The value may vary during power-up. This applies for all V
settings (3.3, 2.5, 1.8, and 1.5 V).
Pin pull-up resistance values will lower if an external source drives the pin higher than V
Drive strength is programmable according to values in
accuracy is within 0.5 pF.
Symbol
Tables 23
Operating Requirements for Altera Devices Data
CC
Input capacitance for user I/O pin
Input capacitance for dual-purpose LVDS/user I/O pin
Input capacitance for dual-purpose V
Input capacitance for dual-purpose DPCLK/user I/O pin.
Input capacitance for CLK pin.
– 38:
rise time is 100 ms, and V
A
= 25 C, V
Detailed power consumption information for Cyclone devices will be
released when available.
The DirectDrive technology and MultiTrack interconnect ensure
predictable performance, accurate simulation, and accurate timing
analysis across all Cyclone device densities and speed grades. This section
describes and specifies the performance, internal, external, and PLL
timing specifications.
All specifications are representative of worst-case supply voltage and
junction temperature conditions.
Preliminary & Final Timing
Timing models can have either preliminary or final status. The Quartus II
software issues an informational message during the design compilation
if the timing models are preliminary.
Cyclone device timing models.
Table 23
CCINT
Parameter
CC
= 1.5 V, and V
may cause permanent damage to a device. Additionally, device
Note (11)
must rise monotonically.
Sheet.
REF
Table 14 on page
CCIO
/user I/O pin.
= 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
Table 39
55.
Cyclone FPGA Family Data Sheet
shows the status of the
Typical
12.0
CCINT
4.0
4.7
4.4
4.7
CCIO
.
and V
CCIO
Unit
are
pF
pF
pF
pF
pF
CCIO
73