EP1C3 ALTERA [Altera Corporation], EP1C3 Datasheet - Page 49

• Manufacturer Part Number: EP1C3
• Description: Cyclone FPGA Family
• Manufacturer: ALTERA [Altera Corporation]

Preliminary Information
Altera Corporation
Figure 31. Control Signal Selection per IOE
Dedicated I/O
Clock [5..0]
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
io_coe
io_csclr
io_caclr
io_cce_out
io_cce_in
io_cclk
In normal bidirectional operation, the designer can use the input register
for input data requiring fast setup times. The input register can have its
own clock input and clock enable separate from the OE and output
registers. The output register can be used for data requiring fast clock-to-
output performance. The OE register is available for fast clock-to-output
enable timing. The OE and output register share the same clock source
and the same clock enable source from the local interconnect in the
associated LAB, dedicated I/O clocks, or the column and row
interconnects.
Figure 32
clk_in
shows the IOE in bidirectional configuration.
clk_out
ce_in
Cyclone FPGA Family Data Sheet
ce_out
aclr/preset
sclr/preset
oe
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