EP1C3 ALTERA [Altera Corporation], EP1C3 Datasheet

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EP1C3

Manufacturer Part Number
EP1C3
Description
Cyclone FPGA Family
Manufacturer
ALTERA [Altera Corporation]
Datasheet

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Introduction
Preliminary
Information
Features...
Note to
(1)
Altera Corporation
DS-CYCLONE-1.1
LEs
M4K RAM blocks (128
Total RAM bits
PLLs
Maximum user I/O pins
March 2003, ver. 1.1
Table 1. Cyclone Device Features
This parameter includes global clock pins.
Table
Feature
1:
(1)
36 bits)
The Cyclone
0.13- m, all-layer copper SRAM process, with densities up to 20,060 logic
elements (LEs) and up to 288 Kbits of RAM. With features like phase-
locked loops (PLLs) for clocking and a dedicated double data rate (DDR)
interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory
requirements, Cyclone devices are a cost-effective solution for data-path
applications. Cyclone devices support various I/O standards, including
LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz,
32-bit peripheral component interconnect (PCI), for interfacing with and
supporting ASSP and ASIC devices. Altera also offers new low-cost serial
configuration devices to configure Cyclone devices.
2,910 to 20,060 LEs, see
Up to 294,912 RAM bits (36,864 bytes)
Supports configuration through low-cost serial configuration device
Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
Support for 66-MHz, 32-bit PCI standard
Low speed (311 Mbps) LVDS I/O support
Up to two PLLs per device provide clock multiplication and phase
shifting
Up to eight global clock lines with six clock resources available per
logic array block (LAB) row
Support for external memory, including DDR SDRAM (133 MHz),
FCRAM, and single data rate (SDR) SDRAM
Support for multiple intellectual property (IP) cores, including
Altera MegaCore functions and Altera Megafunctions Partners
Program (AMPP
59,904
EP1C3
2,910
104
13
1
TM
®
field programmable gate array family is based on a 1.5-V,
SM
78,336
EP1C4
4,000
) megafunctions
301
17
2
Table 1
92,160
EP1C6
5,980
185
20
2
239,616
EP1C12
12,060
249
52
2
FPGA Family
Cyclone
Data Sheet
294,912
EP1C20
20,060
301
64
2
1

Related parts for EP1C3

EP1C3 Summary of contents

Page 1

... Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM Support for multiple intellectual property (IP) cores, including Altera MegaCore functions and Altera Megafunctions Partners SM Program (AMPP ) megafunctions EP1C3 EP1C4 2,910 4,000 13 17 59,904 78,336 ...

Page 2

... TQFP: thin quad flat pack. PQFP: plastic quad flat pack. (2) Cyclone devices support vertical migration within the same package (i.e., designers can migrate between the EP1C3 device in the 144-pin TQFP package and the EP1C6 device in the same package). Table 3. Cyclone QFP & FineLine BGA Package Sizes ...

Page 3

Preliminary Information Table of Contents Altera Corporation Introduction ........................................................................................................1 Features ............................................................................................................... 1 Table of Contents ...............................................................................................3 Functional Description......................................................................................4 Logic Array Blocks.............................................................................................6 Logic Elements ...................................................................................................9 MultiTrack Interconnect .................................................................................17 Embedded Memory.........................................................................................23 Global Clock Network & Phase-Locked Loops...........................................34 I/O Structure ....................................................................................................44 Power Sequencing ...

Page 4

Cyclone FPGA Family Data Sheet Functional Cyclone devices contain a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of Description varying speeds provide signal interconnects between LABs and embedded memory blocks. The logic array consists ...

Page 5

... Preliminary Information Figure 1. Cyclone EP1C12 Device Block Diagram IOEs Logic Array PLL M4K Blocks Table 4. Cyclone Device Resources Device Columns EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 Altera Corporation EP1C12 Device The number of M4K RAM blocks, PLLs, rows, and columns vary per device. ...

Page 6

Cyclone FPGA Family Data Sheet Logic Array Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local interconnect, look-up table (LUT) chain, and register chain connection Blocks lines. The local interconnect transfers signals between LEs in ...

Page 7

Preliminary Information Figure 3. Direct Link Connection Direct link interconnect from left LAB, M4K memory block, PLL, or IOE output Direct link interconnect to left Interconnect Altera Corporation LAB Interconnects The LAB local interconnect can drive LEs within the same ...

Page 8

Cyclone FPGA Family Data Sheet Each LAB can use two clocks and two clock enable signals. Each LAB’s clock and clock enable signals are linked. For example, any particular LAB using the labclk1 signal will also use ...

Page 9

Preliminary Information Logic Elements Figure 5. Cyclone LE LAB Carry-In Carry-In1 addnsub Carry-In0 data1 data2 Look-Up data3 data4 labclr1 labclr2 Asynchronous labpre/aload Clear/Preset/ Load Logic Chip-Wide Reset Clock & Clock Enable Select labclk1 labclk2 labclkena1 labclkena2 Altera Corporation The smallest ...

Page 10

Cyclone FPGA Family Data Sheet Each LE’s programmable register can be configured for operation. Each register has data, true asynchronous load data, clock, clock enable, clear, and asynchronous load/preset inputs. Global signals, general-purpose I/O pins, ...

Page 11

Preliminary Information Altera Corporation addnsub Signal The LE’s dynamic adder/subtractor feature saves logic resources by using one set of LEs to implement both an adder and a subtractor. This feature is controlled by the LAB-wide control signal addnsub. The addnsub ...

Page 12

Cyclone FPGA Family Data Sheet Normal Mode The normal mode is suitable for general logic applications and combinatorial functions. In normal mode, four data inputs from the LAB local interconnect are inputs to a four-input LUT (see Quartus II Compiler ...

Page 13

Preliminary Information Altera Corporation Dynamic Arithmetic Mode The dynamic arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators dynamic arithmetic mode uses four 2-input LUTs configurable as a dynamic adder/subtractor. The first ...

Page 14

Cyclone FPGA Family Data Sheet Figure Dynamic Arithmetic Mode LAB Carry-In Carry-In0 Carry-In1 addnsub (LAB Wide) (1) data1 data2 data3 Carry-Out0 Note to Figure 7: (1) The addnsub signal is tied to the carry input for the ...

Page 15

Preliminary Information Altera Corporation Figure 8 shows the carry-select circuitry in an LAB for a 10-bit full adder. One portion of the LUT generates the sum of two bits using the input signals and the appropriate carry-in bit; the sum ...

Page 16

Cyclone FPGA Family Data Sheet Figure 8. Carry Select Chain LAB Carry- Sum1 A1 LE1 B1 Sum2 A2 LE2 B2 Sum3 A3 LE3 B3 Sum4 A4 LE4 B4 Sum5 A5 LE5 Sum6 A6 LE6 B6 ...

Page 17

Preliminary Information MultiTrack Interconnect Altera Corporation Clear & Preset Logic Control LAB-wide signals control the logic for the register’s clear and preset signals. The LE directly supports an asynchronous clear and preset function. The register preset is achieved through the ...

Page 18

Cyclone FPGA Family Data Sheet The R4 interconnects span four LABs, or two LABs and one M4K RAM block. These resources are used for fast row connections in a four-LAB region. Every LAB has its own set of R4 interconnects ...

Page 19

Preliminary Information Altera Corporation Cyclone devices include an enhanced interconnect structure within LABs for routing LE output to LE input connections faster using LUT chain connections and register chain connections. The LUT chain connection allows the combinatorial output of an ...

Page 20

Cyclone FPGA Family Data Sheet Figure 10. LUT Chain & Register Chain Interconnects The C4 interconnects span four LABs or M4K blocks up or down from a source LAB. Every LAB has its own set of C4 interconnects to drive ...

Page 21

Preliminary Information Figure 11. C4 Interconnect Connections Row Interconnect Adjacent LAB can drive onto neighboring LAB's C4 interconnect Note to Figure 11: (1) Each C4 interconnect can drive either up or down four rows. Altera Corporation Note (1) Local Interconnect ...

Page 22

Cyclone FPGA Family Data Sheet All embedded blocks communicate with the logic array similar to LAB-to- LAB interfaces. Each block (i.e., M4K memory or PLL) connects to row and column interconnects and has local interconnect regions driven by row and ...

Page 23

... Altera Corporation The Cyclone embedded memory consists of columns of M4K memory blocks. EP1C3 and EP1C6 devices have one column of M4K blocks, while EP1C12 and EP1C20 devices have two columns (see total RAM bits per density). Each M4K block can implement various types of memory with or without parity, including true dual-port, simple dual- port, and single-port RAM, ROM, and FIFO buffers ...

Page 24

Cyclone FPGA Family Data Sheet Figure 13. Simple Dual-Port & Single-Port Memory Configurations Note to (1) The memory blocks also enable mixed-width data ports for reading and writing to the RAM ports in dual-port RAM configuration. For example, the memory ...

Page 25

Preliminary Information Altera Corporation When configured as RAM or ROM, the designer can use an initialization file to pre-load the memory contents. Two single-port memory blocks can be implemented in a single M4K block as long as each of the ...

Page 26

Cyclone FPGA Family Data Sheet Data is written into each address location at the falling edge of the clock and read from the address at the rising edge of the clock. The shift register mode logic automatically controls the positive ...

Page 27

Preliminary Information Table 6. M4K RAM Block Configurations (Simple Dual-Port) Read Port 512 8 v 256 16 v 128 32 512 9 256 18 128 36 Table 7. ...

Page 28

Cyclone FPGA Family Data Sheet Byte Enables M4K blocks support byte writes when the write port has a data width of 16, 18, 32 bits. The byte enables allow the input data to be masked so the device ...

Page 29

Preliminary Information Figure 15. M4K RAM Block Control Signals Dedicated 6 LAB Row Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect clock_a Figure 16. M4K RAM Block LAB Row Interface C4 Interconnects Direct link interconnect to adjacent ...

Page 30

Cyclone FPGA Family Data Sheet Independent Clock Mode The M4K memory blocks implement independent clock mode for true dual-port memory. In this mode, a separate clock is available for each port (ports A and B). Clock A controls all registers ...

Page 31

Preliminary Information Figure 18. Input/Output Clock Mode in True Dual-Port Mode 6 LAB Row Clocks 6 data [ ] A D ENA byteena [ ] A D ENA address [ ] D A ENA wren A D clken A ENA ...

Page 32

Cyclone FPGA Family Data Sheet Figure 19. Input/Output Clock Mode in Simple Dual-Port Mode 6 LAB Row Clocks 6 data[ ] address[ ] byteena[ ] wraddress[ ] rden wren outclken inclken inclock outclock Note to Figures 19: (1) All registers ...

Page 33

Preliminary Information Figure 20. Read/Write Clock Mode in Simple Dual-Port Mode 6 LAB Row Clocks 6 data[ ] address[ ] wraddress[ ] byteena[ ] rden wren rdclken wrclken wrclock rdclock Note to Figure 20: (1) All registers shown except the ...

Page 34

Cyclone FPGA Family Data Sheet Figure 21. Single-Port Mode 6 LAB Row Clocks 6 data[ ] address[ ] wren outclken inclken inclock outclock Global Clock Cyclone devices provide a global clock network and up to two PLLs for a complete ...

Page 35

... DPCLK0 Notes to Figure 22: (1) The EP1C3 device in the 100-pin TQFP package has five DPCLK pins (DPCLK2, DPCLK3, DPCLK4, DPCLK6, and DPCLK7). (2) EP1C3 devices only contain one PLL (PLL 1). (3) The EP1C3 device in the 100-pin TQFP package does not have dedicated clock pins CLK1 and CLK3. ...

Page 36

... Cyclone FPGA Family Data Sheet Dual-Purpose Clock Pins Each Cyclone device except the EP1C3 device has eight dual-purpose clock pins, DPCLK[7..0] (two on each I/O bank). EP1C3 devices have five DPCLK pins in the 100-pin TQFP package. These dual-purpose pins can connect to the global clock network (see ...

Page 37

... IO_CLK[5..0] PLLs Cyclone PLLs provide general-purpose clocking with clock multiplication and phase shifting as well as outputs for differential I/O support. Cyclone devices contain two PLLs, except for the EP1C3 device, which contains one PLL. Cyclone FPGA Family Data Sheet I/O Clock Regions LAB Row Clocks labclk[5 ...

Page 38

... Figure 25: (1) The EP1C3 device in the 100-pin TQFP package does not support external outputs or LVDS inputs. The EP1C6 device in the 144-pin TQFP package does not support external output from PLL2. (2) LVDS input is supported via the secondary function of the dedicated clock pins. For PLL 1, the CLK0 pin’s secondary function is LVDSCLK1p and the CLK1 pin’ ...

Page 39

... PLL1_OUT and PLL2_OUT support single-ended or LVDS output. If external output is not required, these pins are available as regular user I/O pins. (4) The EP1C3 device in the 100-pin TQFP package does not support external clock output. The EP1C6 device in the 144-pin TQFP package does not support external clock output from PLL2. Altera Corporation ...

Page 40

... EP1C3 devices in the 100-pin TQFP package do not have dedicated clock pins CLK1 and CLK3. (3) EP1C3 devices in the 100-pin TQFP package do not have the DPCLK0, DPCLK1, or DPCLK5 pins. Clock Multiplication & Division Cyclone PLLs provide clock synthesis for PLL output ports using m/(n pre-scale divider, n, and is then multiplied by the m feedback factor ...

Page 41

Preliminary Information Altera Corporation Each PLL has one pre-scale divider, n, that can range in value from 1 to 32. Each PLL also has one multiply divider, m, that can range in value from 2 to 32. Global clock outputs ...

Page 42

... The external clock outputs do not have their own V supplies. Therefore, to minimize jitter, do not place switching I/O pins next to these output pins. The EP1C3 device in the 100-pin TQFP package does not have dedicated clock output pins. The EP1C6 device in the 144-pin TQFP package only supports dedicated clock outputs from PLL 1. ...

Page 43

Preliminary Information f Altera Corporation Programmable Duty Cycle The programmable duty cycle allows PLLs to generate clock outputs with a variable duty cycle. This feature is supported on each PLL post-scale counter (g0, g1, e). The duty cycle setting is ...

Page 44

Cyclone FPGA Family Data Sheet I/O Structure IOEs support many features, including: Cyclone device IOEs contain a bidirectional I/O buffer and three registers for complete embedded bidirectional single data rate transfer. shows the Cyclone IOE structure. The IOE contains one ...

Page 45

Preliminary Information Altera Corporation Figure 27. Cyclone IOE Structure Logic Array OE Output Combinatorial input (1) Input Note to Figure 27: (1) There are two paths available for combinatorial inputs to the logic array. Each path contains a unique programmable ...

Page 46

Cyclone FPGA Family Data Sheet Figure 28. Row I/O Block Connection to the Interconnect R4 Interconnects LAB Direct Link Interconnect to Adjacent LAB LAB Local Interconnect Notes to Figure 28: (1) The 21 data and control signals consist of three ...

Page 47

Preliminary Information Figure 29. Column I/O Block Connection to the Interconnect 21 Data & Control Signals from Logic Array (1) I/O Block Local Interconnect R4 Interconnects LAB LAB Local Interconnect Notes to Figure 29: (1) The 21 data and control ...

Page 48

Cyclone FPGA Family Data Sheet The pin’s datain signals can drive the logic array. The logic array drives the control and data signals, providing a flexible routing resource. The row or column IOE clocks, io_clk[5..0], provide a dedicated routing resource ...

Page 49

Preliminary Information Figure 31. Control Signal Selection per IOE Dedicated I/O Clock [5..0] io_coe Local Interconnect io_csclr Local Interconnect io_caclr Local Interconnect io_cce_out Local Interconnect io_cce_in Local Interconnect io_cclk Local Interconnect Altera Corporation clk_out clk_in In normal bidirectional operation, the ...

Page 50

Cyclone FPGA Family Data Sheet Figure 32. Cyclone IOE in Bidirectional I/O Configuration ioe_clk[5..0] Column or Row Interconect OE clkout ce_out aclr/prn Chip-Wide Reset comb_datain data_in clkin ce_in The Cyclone device IOE includes programmable delays to ensure zero hold times, ...

Page 51

Preliminary Information Altera Corporation A path in which a pin directly drives a register may require a programmable delay to ensure zero hold time, whereas a path in which a pin drives a register through combinatorial logic may not require ...

Page 52

Cyclone FPGA Family Data Sheet DDR SDRAM & FCRAM Cyclone devices have dedicated circuitry for interfacing with DDR SDRAM. All I/O banks support DDR SDRAM and FCRAM I/O pins. However, the configuration input pins in bank 1 must operate at ...

Page 53

... Note to Table 13: (1) EP1C3 devices in the 100-pin TQFP package do not have any DQ pin groups in I/O bank 1. A programmable delay chain on each DQS pin allows for either a 90° phase shift (for DDR SDRAM 72° phase shift (for FCRAM) which automatically center-aligns input DQS synchronization signals within the data window of their corresponding DQ data signals ...

Page 54

Cyclone FPGA Family Data Sheet Figure 34 through the dedicated circuitry to the logic array. Figure 34. DDR SDRAM & FCRAM Interfacing Register Output Register V CC Output LE GND PLL Phase Shifted -90 ...

Page 55

Preliminary Information Altera Corporation Programmable Drive Strength The output buffer for each Cyclone device I/O pin has a programmable drive strength control for certain I/O standards. The LVTTL and LVCMOS standards have several levels of drive strength that the designer ...

Page 56

Cyclone FPGA Family Data Sheet Slew-Rate Control The output buffer for each Cyclone device I/O pin has a programmable output slew-rate control that can be configured for low noise or high- speed performance. A faster slew rate provides high-speed transitions ...

Page 57

... Notes to Table 15: (1) EP1C3 devices do not support PCI. (2) EP1C3 devices in the 100-pin TQFP package do not support the LVDS I/O standard. (3) This I/O standard is only available on output clock pins (PLL_OUT pins). Altera Corporation Advanced I/O Standard Support Cyclone device IOEs support the following I/O standards: 3.3-V LVTTL/LVCMOS 2 ...

Page 58

Cyclone FPGA Family Data Sheet Figure 35. Cyclone I/O Banks I/O Bank 1 Also Supports the 3.3-V PCI I/O Standard I/O Bank 1 Notes to Figure 35: (1) Figure top view of the silicon die. (2) Figure ...

Page 59

... EP1C20 Note to Table 16: (1) EP1C3 devices in the 100-pin TQFP package do not support the LVDS I/O standard. MultiVolt I/O Interface The Cyclone architecture supports the MultiVolt I/O interface feature, which allows Cyclone devices in all packages to interface with systems of different supply voltages. The devices have one set of V ...

Page 60

Cyclone FPGA Family Data Sheet The Cyclone V supply. If the V and 3.3-V tolerant. The V 1.8-V, 2.5-V, or 3.3-V power supply, depending on the output requirements. The output levels are compatible with systems of the same voltage as ...

Page 61

Preliminary Information Altera Corporation Cyclone devices support reconfiguring the I/O standard settings on the IOE through the JTAG BST chain. The JTAG chain can update the I/O standard for all input and output pins any time before or during user ...

Page 62

Cyclone FPGA Family Data Sheet Table 18. Cyclone JTAG Instructions JTAG Instruction Instruction Code SAMPLE/PRELOAD 00 0000 0101 (1) EXTEST 00 0000 0000 BYPASS 11 1111 1111 USERCODE 00 0000 0111 IDCODE 00 0000 0110 (1) HIGHZ 00 0000 1011 ...

Page 63

... The Cyclone device instruction register length is 10 bits and the USERCODE register length is 32 bits. boundary-scan register length and device IDCODE information for Cyclone devices. Table 19. Cyclone Boundary-Scan Register Length Device EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 IDCODE (32 Bits) Part Number (16 Bits) ...

Page 64

Cyclone FPGA Family Data Sheet Figure 36 Figure 36. Cyclone JTAG Waveforms Table 21 devices. 64 shows the timing requirements for the JTAG signals. TMS TDI t JCP t t JCH JCL TCK t JPZX TDO t JSSU Signal to ...

Page 65

Preliminary Information f SignalTap II Embedded Logic Analyzer Configuration Altera Corporation For more information on JTAG, see the following documents: Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices) Jam Programming & Test Language Specification Cyclone devices ...

Page 66

Cyclone FPGA Family Data Sheet Operating Modes The Cyclone architecture uses SRAM configuration elements that require configuration data to be loaded each time the circuit powers up. The process of physically loading the SRAM data into the device is called ...

Page 67

Preliminary Information Operating Conditions Table 23. Cyclone Device Absolute Maximum Ratings Symbol Parameter V Supply voltage CCINT V CCIO V DC input voltage output current, per pin OUT T Storage temperature STG T Ambient temperature AMB T ...

Page 68

Cyclone FPGA Family Data Sheet Table 24. Cyclone Device Recommended Operating Conditions Symbol Parameter V Supply voltage for internal logic CCINT and input buffers V Supply voltage for output buffers, CCIO 3.3-V operation Supply voltage for output buffers, 2.5-V operation ...

Page 69

Preliminary Information Table 26. LVTTL Specifications Symbol Parameter V Output supply voltage CCIO V High-level input voltage Low-level input voltage IL V High-level output voltage OH V Low-level output voltage OL Table 27. LVCMOS Specifications Symbol Parameter ...

Page 70

Cyclone FPGA Family Data Sheet Table 29. 1.8-V I/O Specifications Symbol Parameter V Output supply voltage CCIO V High-level input voltage Low-level input voltage IL V High-level output voltage OH V Low-level output voltage OL Table 30. ...

Page 71

Preliminary Information Table 32. 3.3-V PCI Specifications Symbol Parameter V Output supply voltage CCIO V High-level input voltage IH V Low-level input voltage IL V High-level output voltage OH V Low-level output voltage OL Table 33. SSTL-2 Class I Specifications ...

Page 72

Cyclone FPGA Family Data Sheet Table 35. SSTL-3 Class I Specifications Symbol Parameter V Output supply voltage CCIO V Termination voltage TT V Reference voltage REF V High-level input voltage IH V Low-level input voltage IL V High-level output voltage ...

Page 73

Preliminary Information Table 38. Cyclone Device Capacitance Symbol C Input capacitance for user I/O pin IO C Input capacitance for dual-purpose LVDS/user I/O pin LVDS C Input capacitance for dual-purpose V VREF C Input capacitance for dual-purpose DPCLK/user I/O pin. ...

Page 74

... Internal timing parameters are specified on a speed grade basis independent of device density. device internal timing microparameters for LEs, IOEs, M4K memory structures, and MultiTrack interconnects. 74 Table 39. Cyclone Device Timing Model Status Device EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 Table 40. LE Internal Timing Microparameter Descriptions Symbol ...

Page 75

Preliminary Information Altera Corporation Table 41. IOE Internal Timing Microparameter Descriptions Symbol t IOE input and output register setup time before clock SU t IOE input and output register hold time after clock H t IOE input and output register ...

Page 76

Cyclone FPGA Family Data Sheet Figure 37 shown in Figure 37. Dual-Port RAM Timing Microparameter Waveform wrclock wren an-1 an wraddress t DATAH din-1 data-in din t DATASU rdclock t WERESU rden rdaddress bn reg_data-out doutn-2 doutn-1 unreg_data-out 76 Table ...

Page 77

Preliminary Information Altera Corporation Internal timing parameters are specified on a speed grade basis independent of device density. timing microparameters for LEs, IOEs, TriMatrix memory structures, DSP blocks, and MultiTrack interconnects. Table 44. LE Internal Timing Microparameters Symbol -6 Min ...

Page 78

Cyclone FPGA Family Data Sheet External Timing Parameters External timing parameters are specified by device density and speed grade. All registers are within the IOE. 78 Table 46. M4K Block Internal Timing Microparameters Symbol -6 Min t M4KRC t M4KWC ...

Page 79

Preliminary Information Altera Corporation Figure 38. External Timing in Cyclone Devices Dedicated Clock All external I/O timing parameters shown are for 3.3-V LVTTL I/O standard with the maximum current strength and fast slew rate. For external I/O timing using standards ...

Page 80

Cyclone FPGA Family Data Sheet Table 48 clock networks. Table 48. Cyclone Global Clock External I/O Timing Parameters Symbol t Setup time for input or bidirectional pin using IOE input INSU register with global clock fed by CLK pin t ...

Page 81

... XZ t 5.283 ZX t 1.195 INSUPLL t 0.000 INHPLL t 0.500 1.900 OUTCOPLL t 3.527 XZPLL t 3.527 ZXPLL Table 50. EP1C3 Row Pin Global Clock External I/O Timing Parameters Symbol -6 Speed Grade Min Max t 2.574 INSU t 0.000 INH t 2.000 3.561 OUTCO 5.147 5.147 ZX t 1.273 ...

Page 82

Cyclone FPGA Family Data Sheet Tables 51 row pins for EP1C4 devices. Note to (1) 82 through 52 show the external timing parameters on column and Table 51. EP1C4 Column Pin Global Clock External I/O Timing Parameters Symbol -6 Speed ...

Page 83

Preliminary Information Altera Corporation Tables 53 through 54 show the external timing parameters on column and row pins for EP1C6 devices. Table 53. EP1C6 Column Pin Global Clock External I/O Timing Parameters Symbol -6 Speed Grade Min Max t 2.432 ...

Page 84

Cyclone FPGA Family Data Sheet Tables 55 row pins for EP1C12 devices. 84 through 56 show the external timing parameters on column and Table 55. EP1C12 Column Pin Global Clock External I/O Timing Parameters Symbol -6 Speed Grade Min Max ...

Page 85

Preliminary Information Altera Corporation Tables 57 through 58 show the external timing parameters on column and row pins for EP1C20 devices. Table 57. EP1C20 Column Pin Global Clock External I/O Timing Parameters Symbol -6 Speed Grade Min Max t 2.226 ...

Page 86

Cyclone FPGA Family Data Sheet Tables 59 row I/O pins for all packages I/O standard is selected other than LVTTL 24 mA with a fast slew rate, add the selected delay to the external t Table 59. Cyclone ...

Page 87

Preliminary Information Table 61. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins Standard LVCMOS 3.3-V LVTTL 2.5-V ...

Page 88

Cyclone FPGA Family Data Sheet Table 62. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part Standard 3.3-V LVTTL 2.5-V LVTTL 2 ...

Page 89

Preliminary Information Table 63. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part I/O Standard 2.5-V LVTTL 1.8-V LVTTL ...

Page 90

... SSTL-3 class II SSTL-2 class I SSTL-2 class II LVDS Note to Tables 59 64: (1) EP1C3 devices do not support the PCI I/O standard. Table 65 delays are controlled with the Quartus II software options listed in the Parameter column. Table 65. Cyclone IOE Programmable Delays on Column Pins Parameter Decrease input delay to On ...

Page 91

Preliminary Information Table 66. Cyclone IOE Programmable Delays on Row Pins Parameter Decrease input delay to On internal cells Small Medium Large Decrease input delay to On input register Increase delay to output On pin Altera Corporation Setting -6 Speed ...

Page 92

... SSTL-2 class I SSTL-2 class II 3.3-V PCI (1) LVDS Tables 67 68: EP1C3 devices do not support the PCI I/O standard. These parameters are only available on row I/O pins. and 70 show the maximum output clock rate for column and Table 69. Cyclone Maximum Output Clock Rate for Column Pins I/O Standard LVTTL 2 ...

Page 93

... LVDS Note to Tables 69 70: (1) EP1C3 devices do not support the PCI I/O standard. These parameters are only available on row I/O pins. Cyclone devices are supported by the Altera Quartus II design software, which provides a comprehensive environment for system-on-a- programmable-chip (SOPC) design. The Quartus II software includes HDL and schematic design entry, compilation and logic synthesis, full simulation and advanced timing analysis, SignalTap II logic analysis, and device configuration ...

Page 94

Cyclone FPGA Family Data Sheet Figure 39. Cyclone Device Packaging Ordering Information EP1C Family Signature EP1C: Cyclone Device Type Package Type T: Thin quad flat pack (TQFP) Q: Plastic quad flat pack (PQFP) F: FineLine ...

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