EP1C3 ALTERA [Altera Corporation], EP1C3 Datasheet - Page 38

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EP1C3

Manufacturer Part Number
EP1C3
Description
Cyclone FPGA Family
Manufacturer
ALTERA [Altera Corporation]
Datasheet

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Cyclone FPGA Family Data Sheet
Figure 25. Cyclone PLL
Notes to
(1)
(2)
(3)
38
LVDSCLK1p (2)
LVDSCLK1n (2)
The EP1C3 device in the 100-pin TQFP package does not support external outputs or LVDS inputs. The EP1C6
device in the 144-pin TQFP package does not support external output from PLL2.
LVDS input is supported via the secondary function of the dedicated clock pins. For PLL 1, the CLK0 pin’s
secondary function is LVDSCLK1p and the CLK1 pin’s secondary function is LVDSCLK1n. For PLL 2, the CLK2 pin’s
secondary function is LVDSCLK2p and the CLK3 pin’s secondary function is LVDSCLK2n.
PFD: phase frequency detector.
CLK0 or
CLK1 or
Figure
25:
Note (1)
Table 9
Cyclone PLL.
Notes to
(1)
(2)
(3)
(4)
Figure 26
Clock multiplication and division
Phase shift
Programmable duty cycle
Number of internal clock outputs
Number of external clock outputs
Table 9. Cyclone PLL Features
÷ n
The m counter ranges from 2 to 32. The n counter and the post-scale counters range
from 1 to 32.
The smallest phase shift is determined by the voltage-controlled oscillator (VCO)
period divided by 8.
For degree increments, Cyclone devices can shift all output frequencies in
increments of 45°. Smaller degree increments are possible depending on the
frequency and divide parameters.
The EP1C3 device in the 100-pin TQFP package does not support external clock
output. The EP1C6 device in the 144-pin TQFP package does not support external
clock output from PLL2.
shows the PLL features in Cyclone devices.
Table
t
shows the PLL global clock connections.
9:
PFD (3)
Feature
t
Charge
Pump
÷ m
Loop
Filter
m/(n
Down to 156-ps increments (2),
Yes
2
One differential or one single-ended
VCO
post-scale counter)
Selectable at Each PLL
VCO Phase Selection
Output Port
PLL Support
Preliminary Information
Figure 25
Altera Corporation
Post-Scale
Counters
÷g0
÷g1
÷e
(1)
shows a
Global clock
Global clock
I/O buffer
(3)
(4)

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