EP1C3 ALTERA [Altera Corporation], EP1C3 Datasheet - Page 80

• Manufacturer Part Number: EP1C3
• Description: Cyclone FPGA Family
• Manufacturer: ALTERA [Altera Corporation]

Cyclone FPGA Family Data Sheet
Notes to
(1)
(2)
80
t
t
t
t
t
t
t
t
t
t
INSU
INH
OUTCO
XZ
ZX
INSUPLL
INHPLL
OUTCOPLL
XZPLL
ZXPLL
Table 48. Cyclone Global Clock External I/O Timing Parameters
Symbol
These timing parameters are sample-tested only.
These timing parameters are for IOE pins using a 3.3-V LVTTL, 24-mA setting. Designers should use the Quartus II
software to verify the external timing for any pin.
Table
48:
Setup time for input or bidirectional pin using IOE input
register with global clock fed by CLK pin
Hold time for input or bidirectional pin using IOE input
register with global clock fed by CLK pin
Clock-to-output delay output or bidirectional pin using IOE
output register with global clock fed by CLK pin
Synchronous column IOE output enable register to output
pin disable delay using global clock fed by CLK pin
Synchronous column IOE output enable register to output
pin enable delay using global clock fed by CLK pin
Setup time for input or bidirectional pin using IOE input
register with global clock fed by Enhanced PLL with default
phase setting
Hold time for input or bidirectional pin using IOE input
register with global clock fed by enhanced PLL with default
phase setting
Clock-to-output delay output or bidirectional pin using IOE
output register with global clock enhanced PLL with default
phase setting
Synchronous column IOE output enable register to output
pin disable delay using global clock fed by enhanced PLL
with default phase setting
Synchronous column IOE output enable register to output
pin enable delay using global clock fed by enhanced PLL
with default phase setting
Table 48
clock networks.
shows the external I/O timing parameters when using global
Parameter
Notes
(1),
C
C
C
C
C
C
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
(2)
= 10 pF
= 10 pF
= 10 pF
= 10 pF
= 10 pF
= 10 pF
Preliminary Information
Conditions
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