EP1C3 ALTERA [Altera Corporation], EP1C3 Datasheet - Page 30

• Manufacturer Part Number: EP1C3
• Description: Cyclone FPGA Family
• Manufacturer: ALTERA [Altera Corporation]

Cyclone FPGA Family Data Sheet
Figure 17. Independent Clock Mode
Note to
(1)
30
byteena
address
data
clken
clock
wren
All registers shown have asynchronous clear ports.
A
A
A
[ ]
[ ]
[ ]
A
A
A
Figure
6
17:
6 LAB Row Clocks
D
ENA
D
ENA
D
ENA
D
ENA
Independent Clock Mode
The M4K memory blocks implement independent clock mode for true
dual-port memory. In this mode, a separate clock is available for each port
(ports A and B). Clock A controls all registers on the port A side, while
clock B controls all registers on the port B side. Each port, A and B, also
supports independent clock enables and asynchronous clear signals for
port A and B registers.
independent clock mode.
Input/Output Clock Mode
Input/output clock mode can be implemented for both the true and
simple dual-port memory modes. On each of the two ports, A or B, one
clock controls all registers for inputs into the memory block: data input,
wren, and address. The other clock controls the block’s data output
registers. Each memory block port, A or B, also supports independent
clock enables and asynchronous clear signals for input and output
registers.
mode.
Q
Q
Q
Q
Generator
Pulse
Write
Figures 18
Note (1)
D
ENA
Data In
Byte Enable A
Address A
Write/Read
Enable
Data Out
Q
A
and
Memory Block
256 ´ 16 (2)
q
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
A
512 ´ 8
[ ]
Figure 17
19
q
B
[ ]
Byte Enable B
show the memory block in input/output clock
Write/Read
Address B
Data Out
Data In
Enable
B
Q
shows an M4K memory block in
ENA
D
Generator
Pulse
Write
Q
Q
Q
Q
ENA
ENA
ENA
ENA
D
D
D
D
Preliminary Information
Altera Corporation
6
data
byteena
address
wren
clken
clock
B
B
B
B
[ ]
B
B
[ ]
[ ]