h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 596

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 17 I
7. Notes on ICDR read at end of master reception
8. Notes on start condition issuance for retransmission
Rev. 3.00 Jan 25, 2006 page 544 of 872
REJ09B0286-0300
Internal clock
To halt reception after completion of a receive operation in master receive mode, set the TRS
bit to 1 and write 0 to BBSY and SCP in ICCR. This changes the SDA pin from low to high
when the SCL pin is high, and generates the stop condition. After this, receive data can be read
by means of an ICDR read, but if data remains in the buffer, the ICDRS receive data will not
be transferred to ICDR, and so it will not be possible to read the second byte of data. If it is
necessary to read the second byte of data, issue the stop condition in master receive mode (i.e.
with the TRS bit cleared to 0). When reading the receive data, first confirm that the BBSY bit
in ICCR is cleared to 0, the stop condition has been generated, and the bus has been released,
then read ICDR with TRS cleared to 0. Note that if the receive data (ICDR data) is read in the
interval between execution of the instruction for issuance of the stop condition (writing 0 to the
BBSY bit in ICCR) and the actual generation of the stop condition, the clock may not be
output correctly in subsequent master transmission. Rewriting of IIC control bits for changing
the operating mode and settings for transmission/reception, such as clearing the MST bit after
master transmit/receive operation has ended, must be done during interval (a) in figure 17.22.
Depending on the timing combination with the start condition issuance and the subsequently
writing data to ICDR, it may not be possible to issue the retransmission condition and the data
transmission after retransmission condition issuance.
BBSY bit
SCL
SDA
2
C Bus Interface (IIC)
Master receive mode
Bit 0
8
Figure 17.22 Notes on Reading Master Receive Data
(write 0 to BBSY and SCP)
for issuing stop condition
Execution of instruction
A
9
disabled period
ICDR read
Confimation of stop
condition issuance
(read BBSY = 0)
Stop condition
(a)
Start condition
issuance
Start condition