h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 217

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

2. Set the start address of the register information at the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception
5. Each time the reception of one byte of data has been completed on the SCI, the RDRF flag in
6. When CRA becomes 0 after 128 data transfers have been completed, the RDRF flag is held at
7.7.2
An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means
of software activation. The transfer source address is H'1000 and the transfer destination address is
H'2000. The vector number is H'60, so the vector address is H'04C0.
1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination
2. Set the start address of the register information at the DTC vector address (H'04C0).
3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated
4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0.
5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this
6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred.
7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear
SCI’s RDR address in SAR, the start address of the RAM area where the data will be received
in DAR, and 128 (H'0080) in CRA. CRB can be set to any value.
complete (RXI) interrupt. Since the generation of a receive error during the SCI reception
operation will disable subsequent reception, the CPU should be enabled to accept receive error
interrupts.
SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is
transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented.
The RDRF flag is automatically cleared to 0.
1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt
handling routine will perform wrap-up processing.
address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz =
0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE =
0). Set the transfer source address (H'1000) in SAR, the transfer destination address (H'2000)
in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.
by software.
indicates that the write failed. This is presumably because an interrupt occurred between steps
3 and 4 and led to a different software activation. To activate this transfer, go back to step 3.
the SWDTE bit to 0 and perform wrap-up processing.
Software Activation
Section 7 Data Transfer Controller (DTC)
Rev. 3.00 Jan 25, 2006 page 165 of 872
REJ09B0286-0300