h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 41

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Figure 17.5
Figure 17.6
Figure 17.7
Figure 17.8
Figure 17.9
Figure 17.10 Slave Receive Mode Operation Timing Example (1) (MLS = ACKB = 0).......... 523
Figure 17.11 Slave Receive Mode Operation Timing Example (2) (MLS = ACKB = 0)......... 524
Figure 17.12 Slave Transmit Mode Operation Timing Example (MLS = 0) ............................. 526
Figure 17.13 IRIC Flag Timing and SCL Control (1)................................................................ 527
Figure 17.14 IRIC Flag Timing and SCL Control (2)................................................................ 528
Figure 17.15 IRIC Flag Timing and SCL Control (3)................................................................ 529
Figure 17.16 Example of Interrupt Flag Timing of Operation Reservation Adapter ................. 530
Figure 17.17 Block Diagram of Noise Canceler ........................................................................ 534
Figure 17.18 Sample Flowchart for Master Transmit Mode...................................................... 536
Figure 17.19 Sample Flowchart for Master Receive Mode ....................................................... 537
Figure 17.20 Sample Flowchart for Slave Receive Mode.......................................................... 538
Figure 17.21 Sample Flowchart for Slave Transmit Mode ........................................................ 539
Figure 17.22 Notes on Reading Master Receive Data ............................................................... 544
Figure 17.23 Flowchart and Timing of Start Condition Issuance for Retransmission ............... 545
Figure 17.24 Stop Condition Issuance Timing........................................................................... 546
Figure 17.25 IRIC Flag Clearing Timing When WAIT = 1....................................................... 546
Figure 17.26 ICDR Read and ICCR Access Timing in Slave Transmit Mode .......................... 547
Figure 17.27 TRS Bit Set Timing in Slave Mode ...................................................................... 548
Figure 17.28 IRIC Flag Clear Timing on WAIT Operation....................................................... 550
Figure 17.29 Diagram of Erroneous Operation when Arbitration Is Lost.................................. 551
Section 18 Universal Serial Bus Interface (USB)
Figure 18.1
Figure 18.2
Figure 18.3
Figure 18.4
Figure 18.5
Figure 18.6
Figure 18.7
Figure 18.8
I
I
Master Receive Mode Operation Timing Example (1)
(MLS = ACKB = 0, WAIT = 1) ........................................................................... 521
Master Receive Mode Operation Timing Example (2)
(MLS = ACKB = 0, WAIT = 1) ........................................................................... 522
Block Diagram of USB......................................................................................... 554
Operation on Receiving a SETUP Token
(When Decode by the Slave CPU Is not Required and When SETICNT = 0) ..... 606
Operation on Receiving a SETUP Token
(When Decode by the Slave CPU Is Required and When SETICNT = 0) ........... 607
Operation on Receiving a SETUP Token
(When Decode by the Slave CPU Is Not Required and When SETICNT = 1) .... 608
Operation on Receiving a SETUP Token
(When Decode by the Slave CPU Is Required and When SETICNT = 1) ........... 609
Operation on Receiving an OUT Token (EP2-OUT: Initial FIFO Is Empty) ....... 610
Operation on Receiving an OUT Token (EP2-OUT: Initial FIFO Is Full) ........... 611
Operation on Receiving an OUT Token (EP5-OUT: Initial FIFO Is Empty) ....... 612
Master Transmit Mode Operation Timing Example (MLS = WAIT = 0) ............ 519
2
2
C Bus Formats (Serial Formats)......................................................................... 516
C Bus Timing ..................................................................................................... 517
Rev. 3.00 Jan 25, 2006 page xli of lii