h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 593

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

17.7
1. In master mode, if an instruction to generate a start condition is immediately followed by an
2. Either of the following two conditions will start the next transfer. Pay attention to these
3. Table 17.11 shows the timing of SCL and SDA outputs in synchronization with the internal
Table 17.11 I
Note:
4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
Data output hold time
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive start and stop conditions, after issuing the instruction that generates the start
condition, read the relevant ports, check that SCL and SDA are both low, then issue the
instruction that generates the stop condition. Note that SCL may not yet have gone low when
BBSY is cleared to 0.
conditions when accessing to ICDR.
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
therefore depends on the system clock cycle t
interface AC timing specifications will not be met with a system clock frequency of less than
5 MHz.
Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from transmit
buffer to shift register)
Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from shift
register to receive buffer)
* 6 t
Usage Notes
cyc
2
C Bus Timing (SCL and SDA Outputs)
when IICX is 0, 12 t
cyc
when 1.
Symbol
t
t
t
t
t
t
t
t
t
SCLO
SCLHO
SCLLO
BUFO
STAHO
STASO
STOSO
SDASO
SDAHO
cyc
, as shown in table 29.10. Note that the I
Output Timing
28 t
0.5 t
0.5 t
0.5 t
0.5 t
1 t
0.5 t
1 t
1 t
3 t
SCLO
SCLLO
SCLL
cyc
cyc
SCLO
SCLO
SCLO
SCLO
SCLO
Rev. 3.00 Jan 25, 2006 page 541 of 872
to 256 t
– (6 t
– 3 t
– 1 t
– 1 t
+ 2 t
Section 17 I
cyc
cyc
cyc
cyc
cyc
cyc
or 12 t
cyc
* )
2
C Bus Interface (IIC)
REJ09B0286-0300
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
2
C bus