h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 39

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Figure 14.6
Figure 14.7
Figure 14.8
Figure 14.9
Section 15 Watchdog Timer (WDT)
Figure 15.1
Figure 15.2
Figure 15.3
Figure 15.4
Figure 15.5
Figure 15.6
Figure 15.7
Figure 15.8
Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
Figure 16.1
Figure 16.2
Figure 16.3
Figure 16.4
Figure 16.5
Figure 16.6
Figure 16.7
Figure 16.8
Figure 16.9
Figure 16.10 Sample Serial Transmission Flowchart................................................................. 426
Figure 16.11 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity,
Figure 16.12 Sample Serial Reception Flowchart (1) ................................................................ 429
Figure 16.12 Sample Serial Reception Flowchart (2) ................................................................ 430
Figure 16.13 Example of Communication Using Multiprocessor Format
Figure 16.14 Sample Multiprocessor Serial Transmission Flowchart........................................ 433
Figure 16.15 Example of SCI Operation in Reception (Example with 8-Bit Data,
Figure 16.16 Sample Multiprocessor Serial Reception Flowchart (1) ....................................... 435
Figure 16.16 Sample Multiprocessor Serial Reception Flowchart (2) ....................................... 436
Figure 16.17 Data Format in Synchronous Communication (LSB-First) .................................. 437
Fall Modification and IHI Synchronization Timing Chart.................................... 366
IVG Signal/IHG Signal/CL4 Signal Timing Chart............................................... 369
CBLANK Output Waveform Generation ............................................................. 372
Block Diagram of WDT ....................................................................................... 374
Watchdog Timer Mode (RST/NMI = 1) Operation .............................................. 380
Interval Timer Mode Operation ............................................................................ 381
OVF Flag Set Timing ........................................................................................... 381
Writing to TCNT and TCSR (WDT_0) ................................................................ 383
Conflict between TCNT Write and Increment...................................................... 384
Sample Circuit for Resetting the System by the RESO Signal ............................. 385
Block Diagram of SCI_1 ...................................................................................... 389
Block Diagram of SCI_0 and SCI_2 .................................................................... 390
Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits) ............................................... 417
Receive Data Sampling Timing in Asynchronous Mode...................................... 419
Relation between Output Clock and Transmit Data Phase
(Asynchronous Mode) .......................................................................................... 420
Basic Clock Examples When Average Transfer Rate Is Selected (1)................... 422
Basic Clock Examples When Average Transfer Rate Is Selected (2)................... 423
Sample SCI Initialization Flowchart..................................................................... 424
Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit) ................................................. 425
One Stop Bit) ........................................................................................................ 427
(Transmission of Data H'AA to Receiving Station A).......................................... 432
Multiprocessor Bit, One Stop Bit) ........................................................................ 434
2fH Modification Timing Chart............................................................................ 364
Output Timing of RESO Signal............................................................................ 382
Rev. 3.00 Jan 25, 2006 page xxxix of lii