h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 215

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

7.5.7
Table 7.6 lists the execution status for a single DTC data transfer, and table 7.7 shows the number
of states required for each execution status.
Table 7.6
N: Block size (initial setting of CRAH and CRAL)
Table 7.7
The number of execution states is calculated from using the formula below. Note that
of all transfers activated by one activation source (the number in which the CHNE bit is set to 1,
plus 1).
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from on-chip ROM to an internal I/O register, then the time required for the
DTC operation is 13 states. The time from activation to the end of data write is 10 states.
Mode
Normal
Repeat
Block transfer
Object to be Accessed
Bus width
Access states
Execution
status
Vector read
Register information
read/write
Byte data read
Word data read
Byte data write
Word data write
Internal operation S
Number of execution states = I · S
Number of DTC Execution States
DTC Execution Status
Number of States Required for Each Execution Status
Vector Read
I
1
1
1
S
S
S
S
S
S
I
J
K
K
L
L
M
On-Chip RAM
(H'(FF)EC00 to
H'(FF)EFFF)
32
1
—
1
1
1
1
1
1
Register Information
Read/Write
J
6
6
6
On-Chip RAM
(On-Chip RAM
other than left)
16
1
—
—
1
1
1
1
1
I
+
(J · S
J
Data Read
K
1
1
N
+ K · S
On-
Chip
ROM
16
1
1
—
1
1
1
1
1
Section 7 Data Transfer Controller (DTC)
Rev. 3.00 Jan 25, 2006 page 163 of 872
K
On-Chip I/O
Registers
8
2
—
—
2
4
2
4
1
+ L · S
16
2
—
—
2
2
2
2
1
Data Write
L
1
1
N
L
) + M · S
External Devices
8
2
4
—
2
4
2
4
1
8
3
6 + 2m
—
3 + m
6 + 2m
3 + m
6 + 2m
1
REJ09B0286-0300
M
Internal
Operations
M
3
3
3
16
2
2
—
2
2
2
2
1
is the sum
16
3
3 + m
—
3 + m
3 + m
3 + m
3 + m
1